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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2020-05-28 17:41:12 -0700 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2020-05-28 17:41:41 -0700 |
| commit | 48ce105e0cfe25559b6ecce928278c2b08952b23 (patch) | |
| tree | ebaeed395c98b01c6bd7a49f2d1bc4a3db3816ae /model/riscv_insts_cdext.sail | |
| parent | e944e9207bc8c2eb31fa85ae66aca381c20dc681 (diff) | |
| download | sail-riscv-48ce105e0cfe25559b6ecce928278c2b08952b23.zip sail-riscv-48ce105e0cfe25559b6ecce928278c2b08952b23.tar.gz sail-riscv-48ce105e0cfe25559b6ecce928278c2b08952b23.tar.bz2 | |
Remove effects on assembly introduced in 1bb74ef9, fix effects on encdec_compressed.
Diffstat (limited to 'model/riscv_insts_cdext.sail')
| -rw-r--r-- | model/riscv_insts_cdext.sail | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/model/riscv_insts_cdext.sail b/model/riscv_insts_cdext.sail index 63277a8..744d199 100644 --- a/model/riscv_insts_cdext.sail +++ b/model/riscv_insts_cdext.sail @@ -19,9 +19,9 @@ function clause execute (C_FLDSP(uimm, rd)) = { } mapping clause assembly = C_FLDSP(uimm, rd) - if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt() + if (sizeof(xlen) == 32 | sizeof(xlen) == 64) <-> "c.fldsp" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_6(uimm) - if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt() + if (sizeof(xlen) == 32 | sizeof(xlen) == 64) /* ****************************************************************** */ union clause ast = C_FSDSP : (bits(6), regidx) @@ -37,9 +37,9 @@ function clause execute (C_FSDSP(uimm, rs2)) = { } mapping clause assembly = C_FSDSP(uimm, rs2) - if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt() + if (sizeof(xlen) == 32 | sizeof(xlen) == 64) <-> "c.fsdsp" ^ spc() ^ reg_name(rs2) ^ sep() ^ hex_bits_6(uimm) - if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt() + if (sizeof(xlen) == 32 | sizeof(xlen) == 64) /* ****************************************************************** */ union clause ast = C_FLD : (bits(5), cregidx, cregidx) @@ -57,9 +57,9 @@ function clause execute (C_FLD(uimm, rsc, rdc)) = { } mapping clause assembly = C_FLD(uimm, rsc, rdc) - if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt() + if (sizeof(xlen) == 32 | sizeof(xlen) == 64) <-> "c.fld" ^ spc() ^ creg_name(rdc) ^ sep() ^ creg_name(rsc) ^ sep() ^ hex_bits_8(uimm @ 0b000) - if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt() + if (sizeof(xlen) == 32 | sizeof(xlen) == 64) /* ****************************************************************** */ union clause ast = C_FSD : (bits(5), cregidx, cregidx) @@ -77,6 +77,6 @@ function clause execute (C_FSD(uimm, rsc1, rsc2)) = { } mapping clause assembly = C_FSD(uimm, rsc1, rsc2) - if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt() + if (sizeof(xlen) == 32 | sizeof(xlen) == 64) <-> "c.fsd" ^ spc() ^ creg_name(rsc1) ^ sep() ^ creg_name(rsc2) ^ sep() ^ hex_bits_8(uimm @ 0b000) - if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt() + if (sizeof(xlen) == 32 | sizeof(xlen) == 64) |