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2026-02-13Add missed stateen checks for the high-half CSRs of `hstateen[0-3]`. (#1546)Prashanth Mundkur1-0/+8
2026-02-10Fix fcvt.s.bf16 NaN-boxing returning wrong canonical QNaN (#1528)Nadime Barhoumi1-1/+7
2026-02-04Validate vector register groups. (#1486)Prashanth Mundkur17-90/+441
2026-02-04Add unratified Zvabd extension (#1478)Tinyueng2-0/+193
2026-02-02Fix typo in directory and module name: Zifenci -> Zifencei. (#1519)Prashanth Mundkur1-0/+0
2026-02-01Add the Zibi extension. (#1507)2026-02-02-e7e6e07tongjiacheng2-0/+55
2026-01-31Add configuration option to handle reserved dynamic rounding modes. (#1491)tongjiacheng1-1/+6
2026-01-31Print registers in AMOCAS reserved message (#1510)tongjiacheng1-5/+5
2026-01-24Add configuration option for reserved behavior: odd number register for RV32Z...2026-01-26-89935a8tongjiacheng1-1/+5
2026-01-24Fix a couple of TODOs now that the VU mode and virtual instruction exceptions...Prashanth Mundkur2-3/+5
2026-01-18Refactor the memory access type. (#1405)Prashanth Mundkur5-58/+56
2026-01-16Add Ssqosid extension (#379)Ved Shanbhogue3-17/+81
2026-01-15Whitespace and alignment fixes for vector files. (#1487)Prashanth Mundkur12-66/+102
2026-01-15Use `bits(1)` and `0b0`/`0b1` consistently in place of `bit` and `bitone`/`bi...Jordan Carlin33-218/+218
2026-01-14Add support for Smstateen and Ssstateen extensions (#910)Nadime Barhoumi4-1/+346
2026-01-08Add configuration option for reserved behavior `pmpcfg with r=0, w=1` (#1422)tongjiacheng1-2/+2
2026-01-04Last remaining refactoring of immediates in encoding clauses for readability....Prashanth Mundkur1-48/+18
2025-12-28Add reserved_behavior.amocas_odd_registers config (#1403)tongjiacheng1-2/+10
2025-12-21Use private keyword in virtual memory code (#1310)Alasdair Armstrong8-30/+30
2025-12-21Add missing `csr_write_callback` in `accrue_fflags` (#1432)Jordan Carlin1-1/+3
2025-12-20Improve handling of reserved fences (#1439)Tim Hutt3-74/+74
2025-12-19Rename `ext_write_vcsr` to just `write_vcsr` (#1438)Prashanth Mundkur1-4/+4
2025-12-19Ensure that `rd` is written by `vset{i}vl{i}` even for illegal and reserved `...Prashanth Mundkur1-5/+11
2025-12-17Add Zdinx to configuration and validate Zfinx-related dependencies (#1431)Nadime Barhoumi2-2/+2
2025-12-08Scatter termination.sail (#1376)Valentin Robert1-0/+4
2025-12-05Use C++ Sail output (#1274)Tim Hutt2-2/+2
2025-12-01Consolidate the indexed vector load and store instructions. (#1410)Prashanth Mundkur2-80/+38
2025-11-28Fix unused variable warnings. (#1409)Prashanth Mundkur8-17/+21
2025-11-27Make the AMO execute more readable. (#1407)Prashanth Mundkur1-59/+56
2025-11-26Add support for Sstvala. (#1397)Prashanth Mundkur1-1/+1
2025-11-25Factor out a `prelude` module. (#1406)Prashanth Mundkur1-0/+52
2025-11-14Greatly simplify the code for reading & writing vector registers/masks (#1213)Tim Hutt8-152/+143
2025-11-12Support a configurable reservation set size. (#1386)Prashanth Mundkur1-0/+2
2025-11-10Add ExecuteAs result for compressed instructions. (#1382)Prashanth Mundkur2-43/+43
2025-11-07Implement a more accurate access type for CSR accesses. (#1369)Prashanth Mundkur2-13/+28
2025-11-06Innocuous typo in constructor name (#1381)Brian Campbell1-1/+1
2025-11-06Rename the AccessType for memory to be more explicit. (#1368)Prashanth Mundkur7-31/+31
2025-10-31Refactor immediates in encoding clauses for readability. (#1364)Prashanth Mundkur7-71/+97
2025-10-30Unify the handling logic for scalar and vector multiplication. (#1299)KotorinMinami4-35/+29
2025-10-21Add gating for vector instructions. (#1170)Wenyu Huang13-138/+308
2025-10-18Improve float classify code (#1288)Tim Hutt5-130/+71
2025-10-15Add wavedrom annotations for some instruction encodings. (#1337)Prashanth Mundkur27-16/+162
2025-10-14Simplify sew/lmul_pow_val (#1331)Tim Hutt2-28/+12
2025-10-13Add support for Zvfbfwma extension (#1185)Nadime Barhoumi3-3/+116
2025-10-09Reduce duplication in vsetvl-type instructions (#1286)Tim Hutt1-106/+63
2025-10-09Add support for Zvfbfmin extension (#1184)Nadime Barhoumi1-0/+109
2025-10-09Remove redundant parentheses around instruction arguments in execute clauses....Prashanth Mundkur41-333/+333
2025-10-09Remove monomorphic `val` declarations by moving types into the function signa...Prashanth Mundkur15-263/+138
2025-10-08Some fixes for documentation inclusion of scalar and vector crypto functions....Prashanth Mundkur2-121/+93
2025-10-08Fix inconsistent capitalization in bitvector literal (#1320)Jordan Carlin1-1/+1
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