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2019-02-20Add ELF architecture checks to the loaders in the OCaml and C emulators.Prashanth Mundkur1-1/+1
2019-02-19Adjust Makefile to use an ARCH argument. Undo xlen guards in riscv_analysis,...Prashanth Mundkur1-10/+47
2019-02-13Add Sv32 and Sv48 by essentially copying Sv39.Prashanth Mundkur1-1/+3
2019-02-13Pull out the Sv39 and its TLB into separate files.Prashanth Mundkur1-1/+1
2019-02-12Start extracting bits of vmem that should be common to RV32, and add some def...Prashanth Mundkur1-2/+4
2019-02-11Fix xlen variable name.Prashanth Mundkur1-1/+1
2019-02-11More refactoring for RV32Prashanth Mundkur1-2/+2
2019-02-08Start parameterizing definitions by xlen, which is currently still 64.Prashanth Mundkur1-2/+2
2019-02-08Split out the mapping prelude into its own file.Prashanth Mundkur1-5/+7
2019-01-31Fix riscv_isa_build Makefile targetThomas Bauereiss1-1/+2
2019-01-29Update Makefile.Prashanth Mundkur1-1/+1
2019-01-29Add CSRs for the 'N' extension arch state and expose to CSR read/write.Prashanth Mundkur1-1/+1
2019-01-29Factor the _sys functionality into separate files for architectural state and...Prashanth Mundkur1-2/+4
2019-01-29Added riscv_rmem that generates the lem files for rmem (which are different f...Shaked Flur1-4/+19
2019-01-25Factor out each extension into separate files, do some minor cleanup.Prashanth Mundkur1-3/+4
2019-01-22Build HOL definitions by defaultThomas Bauereiss1-1/+1
2019-01-22Add build Makefile targets for prover backendsThomas Bauereiss1-3/+36
2019-01-21Output auxiliary Isabelle theories into generated_definitions/isabelleThomas Bauereiss1-6/+9
2019-01-16More reorg.Prashanth Mundkur1-71/+71
2019-01-16Properly locate generated latex.Prashanth Mundkur1-1/+2
2019-01-16Make it clearer that the outer c,ocaml sub-dirs contain supporting files for ...Prashanth Mundkur1-27/+28
2019-01-15Ensure generated model sub-dirs are created.Prashanth Mundkur1-0/+12
2019-01-15Make the names of the OCaml and C simulators more similar, with C being the d...Prashanth Mundkur1-9/+9
2019-01-14Reorganize directory structure.Prashanth Mundkur1-95/+89
2019-01-02Add termination measures to get patch-free Coq outputBrian Campbell1-2/+3
2018-12-20Commit changes from rems-project/sail@b167a59affdb6428fa0656a092b335a3a6899d5...Robert Norton1-0/+6
2018-12-17Fix stray - in Makefile accidentally introduced by previous commit.Robert Norton1-1/+1
2018-12-17Add build time COVERAGE option to build with gcc coverage. Attempt to choose ...Robert Norton1-6/+17
2018-11-30Update default make targets and README.Prashanth Mundkur1-3/+9
2018-11-30Disable line-of-code counting which is broken if SAIL_DIR is not set.Robert Norton1-2/+2
2018-11-30Split out riscv from sail repo using git-filter-branch.Robert Norton1-14/+27
2018-11-29RISC-V: more tidying up of the Spike interface.Prashanth Mundkur1-12/+12
2018-11-12Add RVFI DII version of the RISC-V simulator for TestRIGBrian Campbell1-0/+9
2018-10-23RISC-V: separate jalr execute clause for seq model and rmem.Prashanth Mundkur1-3/+12
2018-10-23RISC-V: Initial splitting of instructions across multiple files.Prashanth Mundkur1-1/+3
2018-10-23RISC-V: Allow Spike linkage to be conditionally enabled.Prashanth Mundkur1-5/+13
2018-10-23RISC-V: An initial C Sail model linked against Spike for testing.Prashanth Mundkur1-0/+12
2018-10-23RISC-V: Refactor c platform bits.Prashanth Mundkur1-2/+3
2018-09-04C: Tweaks to RISC-V to get compiling to CAlasdair Armstrong1-1/+2
2018-08-31Some C stubs for platform bits for RISC-V.Prashanth Mundkur1-3/+5
2018-08-30Annotate the RISC-V prelude for C builtins.Prashanth Mundkur1-4/+4
2018-08-30Add a C header containing declarations needed by RISC-V.Prashanth Mundkur1-3/+3
2018-08-29C: Fix some issues with tuples as arguments to polymorphic constructorsAlasdair Armstrong1-2/+6
2018-08-28Adapt theory imports for Isabelle 2018Thomas Bauereiss1-2/+2
2018-08-13Add constraints to RISC-V duopod, makefile rulesBrian Campbell1-0/+4
2018-08-13Basic Coq support for RISC-VBrian Campbell1-0/+9
2018-07-27Add a riscv latex target.Prashanth Mundkur1-0/+3
2018-07-10Start adding c-backend bits for riscv.Prashanth Mundkur1-0/+3
2018-07-10Make HOL build properly again for all of the modelsBrian Campbell1-1/+2
2018-07-09add riscv_analysis.sail to SAIL_SRCSJon French1-1/+1
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