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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-02-13 17:42:20 -0800 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-02-13 17:42:20 -0800 |
| commit | 79339748366f25c1dad7d2e71a04046579e17867 (patch) | |
| tree | 35c4355cfcb9f0b4b969d9ab54ccb2ae91e462a4 /Makefile | |
| parent | 760fb55e59bee9f987d7445e85a27e2c6a8781a8 (diff) | |
| download | sail-riscv-79339748366f25c1dad7d2e71a04046579e17867.zip sail-riscv-79339748366f25c1dad7d2e71a04046579e17867.tar.gz sail-riscv-79339748366f25c1dad7d2e71a04046579e17867.tar.bz2 | |
Pull out the Sv39 and its TLB into separate files.
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -7,7 +7,7 @@ SAIL_RMEM_INST_SRCS = riscv_insts_begin.sail $(SAIL_RMEM_INST) riscv_insts_end.s SAIL_SYS_SRCS = riscv_csr_map.sail riscv_sys_regs.sail riscv_next_regs.sail riscv_next_control.sail riscv_sys_control.sail -SAIL_VM_SRCS = riscv_vmem_common.sail riscv_vmem.sail +SAIL_VM_SRCS = riscv_vmem_common.sail riscv_vmem_tlb.sail riscv_vmem_sv39.sail riscv_vmem.sail # non-instruction sources PRELUDE = prelude.sail prelude_mapping.sail riscv_xlen.sail prelude_mem.sail |