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2018-11-30Add some initial info about the Sail files to the readme.Prashanth Mundkur1-8/+41
2018-11-30Mention a brief current status in readme.Prashanth Mundkur1-0/+3
2018-11-30Add another README detail.Prashanth Mundkur1-1/+3
2018-11-30More readme edits.Prashanth Mundkur1-3/+22
2018-11-30Minor readme edit.Prashanth Mundkur1-4/+3
2018-11-30Update default make targets and README.Prashanth Mundkur2-11/+37
2018-11-30Make rvfi-dii sessions end cleanlyBrian Campbell1-4/+12
2018-11-30Fix memory leaks in rvfi-dii modeBrian Campbell1-0/+2
2018-11-30Disable line-of-code counting which is broken if SAIL_DIR is not set.Robert Norton1-2/+2
2018-11-30Tweak README.Robert Norton1-0/+5
2018-11-30Move readme to .md fileRobert Norton1-0/+0
2018-11-30Re-import tests from sail repo.Robert Norton372-0/+127624
2018-11-30Add gitignoreRobert Norton1-5/+48
2018-11-30Add licence.Robert Norton1-0/+52
2018-11-30Split out riscv from sail repo using git-filter-branch.Robert Norton1-14/+27
2018-11-29RISC-V: more tidying up of the Spike interface.Prashanth Mundkur2-23/+22
2018-11-29RISC-V: implement WFI in the platform model.Prashanth Mundkur2-2/+14
2018-11-29RISC-V: factor the execution trace.Prashanth Mundkur12-54/+126
2018-11-29RISC-V: no ldu for rv64iBrian Campbell1-3/+3
2018-11-29RISC-V: properly set mstatus.FS in absence of floating-point support.Prashanth Mundkur1-0/+5
2018-11-29RISC-V: minor cleanup of the spike interface.Prashanth Mundkur1-40/+45
2018-11-29RISC-V: add some missing constraints on compressed instruction encodingsBrian Campbell1-3/+3
2018-11-29RISC-V: add checks for misaligned targets to jumps and branchesBrian Campbell3-11/+29
2018-11-29Merge branch 'rvfi-dii' into sail2Brian Campbell8-6/+448
2018-11-27Fix memory leak in string_of_bitsAlasdair Armstrong1-0/+1
2018-11-21RISC-V: allow platform ram size to be configurable.Prashanth Mundkur4-13/+37
2018-11-20Minor coq updatesBrian Campbell1-13/+14
2018-11-19Merge branch 'latex' into sail2Robert Norton0-0/+0
2018-11-14Add option to turn off RISC-V compressed instruction supportBrian Campbell3-19/+33
2018-11-14Fix memory map in RVFI-DII modeBrian Campbell1-5/+9
2018-11-12rvfi_dii: take port number with optionBrian Campbell1-4/+6
2018-11-12Add RVFI DII version of the RISC-V simulator for TestRIGBrian Campbell8-3/+425
2018-11-09RISC-V: add missed c.ebreak instructionPrashanth Mundkur1-0/+10
2018-11-08RISC-V: fix a typo-induced bug in updating the PTE.Prashanth Mundkur1-1/+1
2018-11-07RISC-V: fix assembly mappings for lr/sc.Prashanth Mundkur1-2/+2
2018-11-07Move inline forall in function definitionsAlasdair Armstrong2-13/+13
2018-11-07Move inline forall in function definitionsAlasdair Armstrong2-13/+13
2018-11-07RISC-V: add some consistency checks when run with spike.Prashanth Mundkur1-2/+17
2018-10-23RISC-V: use stderr for terminal output in OCaml backend.Prashanth Mundkur2-1/+24
2018-10-23RISC-V: separate jalr execute clause for seq model and rmem.Prashanth Mundkur4-19/+37
2018-10-23RISC-V: Initial splitting of instructions across multiple files.Prashanth Mundkur4-38/+37
2018-10-23RISC-V: Allow the C platform to get the DTB from a file, so that OS boot is p...Prashanth Mundkur1-22/+100
2018-10-23RISC-V: add cli option to dump the platform device-tree.Prashanth Mundkur1-7/+35
2018-10-23RISC-V: Add a platform knob to control mtval contents on illegal instruction ...Prashanth Mundkur13-23/+52
2018-10-23RISC-V: various fixesPrashanth Mundkur3-2/+4
2018-10-23RISC-V: fix: sstatus.SD depends on .XS and .FS.Prashanth Mundkur1-1/+5
2018-10-23RISC-V: adjust main loop for the non-spike case.Prashanth Mundkur1-10/+11
2018-10-23RISC-V: implement terminal output for C platform.Prashanth Mundkur4-7/+52
2018-10-23RISC-V: tick the clock in the C platform.Prashanth Mundkur4-2/+20
2018-10-23RISC-V: Add device tree blob into rom, currently only when linked against spike.Prashanth Mundkur1-3/+17
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