Add option to turn off RISC-V compressed instruction support

3 files changed, 33 insertions, 19 deletions

diff --git a/main_rvfi.sail b/main_rvfi.sail
index e1469f7..0ba4acf 100644
--- a/main_rvfi.sail
+++ b/main_rvfi.sail
@@ -2,20 +2,24 @@
 
 val rvfi_fetch : unit -> FetchResult effect {escape, rmem, rreg, wmv, wreg}
 
-function rvfi_fetch() = {
-  let i = rvfi_instruction.rvfi_insn();
-  rvfi_exec->rvfi_order() = minstret;
-  rvfi_exec->rvfi_pc_rdata() = PC;
-  rvfi_exec->rvfi_insn() = zero_extend(i,64);
-  /* TODO: should we write these even if they're not really registers? */
-  rvfi_exec->rvfi_rs1_data() = X(i[19 .. 15]);
-  rvfi_exec->rvfi_rs2_data() = X(i[24 .. 20]);
-  rvfi_exec->rvfi_rs1_addr() = zero_extend(i[19 .. 15],8);
-  rvfi_exec->rvfi_rs2_addr() = zero_extend(i[24 .. 20],8);
-  if (i[1 .. 0] == 0b11)
-  then F_Base(i)
-  else F_RVC(i[15 .. 0])
-}
+function rvfi_fetch() =
+  /* check for legal PC */
+  if (PC[0] != 0b0 | (PC[1] != 0b0 & (~ (haveRVC()))))
+  then F_Error(E_Fetch_Addr_Align, PC)
+  else {
+    let i = rvfi_instruction.rvfi_insn();
+    rvfi_exec->rvfi_order() = minstret;
+    rvfi_exec->rvfi_pc_rdata() = PC;
+    rvfi_exec->rvfi_insn() = zero_extend(i,64);
+    /* TODO: should we write these even if they're not really registers? */
+    rvfi_exec->rvfi_rs1_data() = X(i[19 .. 15]);
+    rvfi_exec->rvfi_rs2_data() = X(i[24 .. 20]);
+    rvfi_exec->rvfi_rs1_addr() = zero_extend(i[19 .. 15],8);
+    rvfi_exec->rvfi_rs2_addr() = zero_extend(i[24 .. 20],8);
+    if (i[1 .. 0] == 0b11)
+    then F_Base(i)
+    else F_RVC(i[15 .. 0])
+  }
 
 // This should be kept in sync with the normal step - at the moment the only
 // changes are to replace fetch by rvfi_fetch and record the next PC.
diff --git a/riscv_sail.h b/riscv_sail.h
index ba052af..424b64b 100644
--- a/riscv_sail.h
+++ b/riscv_sail.h
@@ -6,6 +6,9 @@ typedef int unit;
 #define UNIT 0
 typedef uint64_t mach_bits;
 
+struct zMisa {mach_bits zMisa_chunk_0;};
+struct zMisa zmisa;
+
 void model_init(void);
 void model_fini(void);
 
@@ -14,6 +17,8 @@ unit zinit_sys(unit);
 bool zstep(sail_int);
 unit ztick_clock(unit);
 unit ztick_platform(unit);
+unit z_set_Misa_C(struct zMisa*, mach_bits);
+
 #ifdef RVFI_DII
 unit zrvfi_set_instr_packet(mach_bits);
 mach_bits zrvfi_get_cmd(unit);
@@ -47,6 +52,3 @@ struct zMcause {mach_bits zMcause_chunk_0;};
 struct zMcause zmcause, zscause;
 
 extern mach_bits zminstret;
-
-struct zMisa {mach_bits zMisa_chunk_0;};
-struct zMisa zmisa;
diff --git a/riscv_sim.c b/riscv_sim.c
index 3a4b66e..27d8a70 100644
--- a/riscv_sim.c
+++ b/riscv_sim.c
@@ -42,6 +42,7 @@ struct tv_spike_t;
 #define CSR_MIP 0x344
 
 static bool do_dump_dts = false;
+static bool disable_compressed = false;
 struct tv_spike_t *s = NULL;
 char *term_log = NULL;
 char *dtb_file = NULL;
@@ -59,6 +60,7 @@ size_t spike_dtb_len = 0;
 static struct option options[] = {
   {"enable-dirty",                no_argument,       0, 'd'},
   {"enable-misaligned",           no_argument,       0, 'm'},
+  {"disable-compressed",          no_argument,       0, 'C'},
   {"mtval-has-illegal-inst-bits", no_argument,       0, 'i'},
   {"dump-dts",                    no_argument,       0, 's'},
   {"device-tree-blob",            required_argument, 0, 'b'},
@@ -137,7 +139,7 @@ char *process_args(int argc, char **argv)
 {
   int c, idx = 1;
   while(true) {
-    c = getopt_long(argc, argv, "dmsb:t:v:hr:", options, &idx);
+    c = getopt_long(argc, argv, "dmCsb:t:v:hr:", options, &idx);
     if (c == -1) break;
     switch (c) {
     case 'd':
@@ -146,6 +148,9 @@ char *process_args(int argc, char **argv)
     case 'm':
       rv_enable_misaligned = true;
       break;
+    case 'C':
+      disable_compressed = true;
+      break;
     case 'i':
       rv_mtval_has_illegal_inst_bits = true;
     case 's':
@@ -322,6 +327,8 @@ void init_sail(uint64_t elf_entry)
   } else
 #endif
   init_sail_reset_vector(elf_entry);
+  if (disable_compressed)
+    z_set_Misa_C(&zmisa, 0);
 }
 
 int init_check(struct tv_spike_t *s)
@@ -476,7 +483,8 @@ void run_sail(void)
       if (stepped) {
         need_instr = true;
         rvfi_send_trace();
-      }
+      } else
+        need_instr = false;
     } else
 #endif
     { /* run a Sail step */