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authorPrashanth Mundkur <prashanth.mundkur@gmail.com>2018-10-02 12:03:23 -0700
committerPrashanth Mundkur <prashanth.mundkur@gmail.com>2018-10-23 15:32:15 -0700
commit1d78e6c76df8fa1cdf961f208035bab849ad11f8 (patch)
treee648f8150618b0bdcdc6705c5fd670b261ba9915
parent8fc234346db27cd0fe9634b1c05f0922fb86b720 (diff)
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RISC-V: adjust main loop for the non-spike case.
-rw-r--r--riscv_sim.c21
1 files changed, 11 insertions, 10 deletions
diff --git a/riscv_sim.c b/riscv_sim.c
index fc732e8..17e426e 100644
--- a/riscv_sim.c
+++ b/riscv_sim.c
@@ -300,23 +300,24 @@ void run_sail(void)
fprintf(stdout, "Sail done (exit-code %ld), but not Spike!\n", zhtif_exit_code);
exit(1);
}
- /* check exit code */
- if (zhtif_exit_code == 0)
- fprintf(stdout, "SUCCESS\n");
- else
- fprintf(stdout, "FAILURE: %ld\n", zhtif_exit_code);
} else {
if (spike_done) {
fprintf(stdout, "Spike done, but not Sail!\n");
exit(1);
}
-
- if (!compare_states(s)) {
- diverged = true;
- break;
- }
+ }
+ if (!compare_states(s)) {
+ diverged = true;
+ break;
}
#endif
+ if (zhtif_done) {
+ /* check exit code */
+ if (zhtif_exit_code == 0)
+ fprintf(stdout, "SUCCESS\n");
+ else
+ fprintf(stdout, "FAILURE: %ld\n", zhtif_exit_code);
+ }
if (insn_cnt == rv_insns_per_tick) {
insn_cnt = 0;