diff options
Diffstat (limited to 'model/riscv_insts_zicsr.sail')
| -rw-r--r-- | model/riscv_insts_zicsr.sail | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/model/riscv_insts_zicsr.sail b/model/riscv_insts_zicsr.sail index 425f7a3..8953ad4 100644 --- a/model/riscv_insts_zicsr.sail +++ b/model/riscv_insts_zicsr.sail @@ -137,6 +137,15 @@ function readCSR csr : csreg -> xlenbits = { (0xB80, 32) => mcycle[63 .. 32], (0xB82, 32) => minstret[63 .. 32], + /* vector */ + (0x008, _) => zero_extend(vstart), + (0x009, _) => zero_extend(vxsat), + (0x00A, _) => zero_extend(vxrm), + (0x00F, _) => zero_extend(vcsr.bits()), + (0xC20, _) => vl, + (0xC21, _) => vtype.bits(), + (0xC22, _) => vlenb, + /* trigger/debug */ (0x7a0, _) => ~(tselect), /* this indicates we don't have any trigger support */ @@ -250,6 +259,15 @@ function writeCSR (csr : csreg, value : xlenbits) -> unit = { /* user mode: seed (entropy source). writes are ignored */ (0x015, _) => write_seed_csr(), + /* vector */ + (0x008, _) => { let vstart_length = get_vlen_pow(); vstart = zero_extend(16, value[(vstart_length - 1) .. 0]); Some(zero_extend(vstart)) }, + (0x009, _) => { vxsat = value[0 .. 0]; Some(zero_extend(vxsat)) }, + (0x00A, _) => { vxrm = value[1 .. 0]; Some(zero_extend(vxrm)) }, + (0x00F, _) => { vcsr->bits() = value[2 ..0]; Some(zero_extend(vcsr.bits())) }, + (0xC20, _) => { vl = value; Some(vl) }, + (0xC21, _) => { vtype->bits() = value; Some(vtype.bits()) }, + (0xC22, _) => { vlenb = value; Some(vlenb) }, + _ => ext_write_CSR(csr, value) }; match res { |