RISC-V Vector Extension Support

This PR adds the following:

General Framework and Configurations:

* Introduced the V extension's general framework and configuration setting instructions.
* Updated model/riscv_insts_vext_vset.sail and effect matching functions in riscv_vlen.sail.
* Addressed code formatting issues and made revisions post the Nov 22 meeting.
* Co-authored by Nicolas Brunie and Jessica Clarke.

Vector Load/Store Instructions:

* Integrated vector load and store instructions.
* Enhanced the implementation of SEW, LMUL, VLEN and removed real numbers from the code.
* Updated vstart settings and removed unnecessary assert statements.
* Rectified bugs in vleff instructions and overhauled coding styles.
* Incorporated guards for vector encdec clauses and optimized memory access post vector load/store failures.

Vector Integer/Fixed-Point Instructions:

* Added vector integer/fixed-point arithmetic and mask instructions.
* Improved vector EEW and EMUL checking functions and introduced illegal instruction check functions.
* Fine-tuned code formatting for vector instruction checks.

Vector Floating-Point Instructions:

* Rolled out vector floating-point instructions and updated their conversion counterparts.
* Refreshed copyright headers specific to the vector extension code.

Vector Reduction and Mask Instructions:

* Integrated vector mask and reduction instructions.
* Addressed register overlap checks for vector mask instructions.

Miscellaneous Enhancements and Fixes:

* Updated vector CSR vtype.vill settings and judgements.
* Systematized patterns for vector illegal instruction checks.
* Rectified issues in vector load/store and reduction operations.
* Purged redundant elements from the V extension code and vector floating-point functions.
* Cleaned up softfloat makefiles and renamed EXTZ and EXTS within the V extension code.
* Addressed a clang-format check issue and NaN boxing anomalies. Provided annotations for pending RVV configurations.
* Initialized default VLEN value and set vlenb CSR.
* Set constraints for vector variable initialization and added mstatus.VS settings specific to the vector extension.

1 files changed, 18 insertions, 0 deletions

diff --git a/model/riscv_insts_zicsr.sail b/model/riscv_insts_zicsr.sail
index 425f7a3..8953ad4 100644
--- a/model/riscv_insts_zicsr.sail
+++ b/model/riscv_insts_zicsr.sail
@@ -137,6 +137,15 @@ function readCSR csr : csreg -> xlenbits = {
     (0xB80, 32) => mcycle[63 .. 32],
     (0xB82, 32) => minstret[63 .. 32],
 
+    /* vector */
+    (0x008, _) => zero_extend(vstart),
+    (0x009, _) => zero_extend(vxsat),
+    (0x00A, _) => zero_extend(vxrm),
+    (0x00F, _) => zero_extend(vcsr.bits()),
+    (0xC20, _) => vl,
+    (0xC21, _) => vtype.bits(),
+    (0xC22, _) => vlenb,
+
     /* trigger/debug */
     (0x7a0,  _) => ~(tselect),  /* this indicates we don't have any trigger support */
 
@@ -250,6 +259,15 @@ function writeCSR (csr : csreg, value : xlenbits) -> unit = {
     /* user mode: seed (entropy source). writes are ignored */
     (0x015,  _) => write_seed_csr(),
 
+    /* vector */
+    (0x008, _) => { let vstart_length = get_vlen_pow(); vstart = zero_extend(16, value[(vstart_length - 1) .. 0]); Some(zero_extend(vstart)) },
+    (0x009, _) => { vxsat = value[0 .. 0]; Some(zero_extend(vxsat)) },
+    (0x00A, _) => { vxrm = value[1 .. 0]; Some(zero_extend(vxrm)) },
+    (0x00F, _) => { vcsr->bits() = value[2 ..0]; Some(zero_extend(vcsr.bits())) },
+    (0xC20, _) => { vl = value; Some(vl) },
+    (0xC21, _) => { vtype->bits() = value; Some(vtype.bits()) },
+    (0xC22, _) => { vlenb = value; Some(vlenb) },
+
     _           => ext_write_CSR(csr, value)
   };
   match res {