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-rw-r--r--Makefile6
1 files changed, 2 insertions, 4 deletions
diff --git a/Makefile b/Makefile
index f7a4a3e..c6ce332 100644
--- a/Makefile
+++ b/Makefile
@@ -10,21 +10,19 @@ endif
# Currently, we only have F with RV32, and both F and D with RV64.
ifeq ($(ARCH),RV32)
SAIL_XLEN := riscv_xlen32.sail
- SAIL_FLEN := riscv_flen_F.sail
else ifeq ($(ARCH),RV64)
SAIL_XLEN := riscv_xlen64.sail
- SAIL_FLEN := riscv_flen_D.sail
else
$(error '$(ARCH)' is not a valid architecture, must be one of: RV32, RV64)
endif
+SAIL_FLEN := riscv_flen_D.sail
+
# Instruction sources, depending on target
SAIL_CHECK_SRCS = riscv_addr_checks_common.sail riscv_addr_checks.sail riscv_misa_ext.sail
SAIL_DEFAULT_INST = riscv_insts_base.sail riscv_insts_aext.sail riscv_insts_cext.sail riscv_insts_mext.sail riscv_insts_zicsr.sail riscv_insts_next.sail riscv_insts_hints.sail
SAIL_DEFAULT_INST += riscv_insts_fext.sail riscv_insts_cfext.sail
-ifeq ($(ARCH),RV64)
SAIL_DEFAULT_INST += riscv_insts_dext.sail riscv_insts_cdext.sail
-endif
SAIL_DEFAULT_INST += riscv_insts_zkn.sail
SAIL_DEFAULT_INST += riscv_insts_zks.sail