diff options
| author | Jessica Clarke <jrtc27@jrtc27.com> | 2021-10-22 15:15:00 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-10-22 15:15:00 +0100 |
| commit | 9b38e33c766c7c0397b9d51bf91544db391be670 (patch) | |
| tree | aee1fe8abd89feb13d924f7f39f346478e0dfd24 /Makefile | |
| parent | 1c7584bb501bb6d4cbc3b95cb22e008220fb537a (diff) | |
| download | sail-riscv-9b38e33c766c7c0397b9d51bf91544db391be670.zip sail-riscv-9b38e33c766c7c0397b9d51bf91544db391be670.tar.gz sail-riscv-9b38e33c766c7c0397b9d51bf91544db391be670.tar.bz2 | |
Support D extension on RV32 (#108)
* Use bool for floating point comparison result
Using bits_WU (bits(32)) or bits_LU (bits(64)) makes no sense, these are
just boolean values, and having fixed-width types is a pain for
suporting RV32D (since RV32D would need to truncate, but RV128D would
need to extend). Instead represent these as an actual bool to match what
the values really are. This could be done with bits(1) but the value is
logically a boolean (like the built-in integer comparison operators) not
a bit vector of length one so we convert to bool and back for a cleaner
interface.
* Support compiling RV32F with flen == 64
The code conflated flen and xlen; deconflating them and adding suitable
assertions (rather than silently retiring as a no-op that doesn't bump
instret) ensures that it can be compiled for RV32 with flen set to 64.
Whilst here, add the extensions and truncations that would be needed for
RV128F.
Note that there are already suitable guards on the decode clauses to
ensure these instructions are illegal on RV32.
* Support compiling RV32D
This copies various bits of XLEN generality from the F code.
* Support RV32D loads/stores
* Correctly initialise misa.D based on flen not xlen
* Makefile: Enable D extension for RV32
This now works so can be enabled.
* test: Enable RV32D tests
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 6 |
1 files changed, 2 insertions, 4 deletions
@@ -10,21 +10,19 @@ endif # Currently, we only have F with RV32, and both F and D with RV64. ifeq ($(ARCH),RV32) SAIL_XLEN := riscv_xlen32.sail - SAIL_FLEN := riscv_flen_F.sail else ifeq ($(ARCH),RV64) SAIL_XLEN := riscv_xlen64.sail - SAIL_FLEN := riscv_flen_D.sail else $(error '$(ARCH)' is not a valid architecture, must be one of: RV32, RV64) endif +SAIL_FLEN := riscv_flen_D.sail + # Instruction sources, depending on target SAIL_CHECK_SRCS = riscv_addr_checks_common.sail riscv_addr_checks.sail riscv_misa_ext.sail SAIL_DEFAULT_INST = riscv_insts_base.sail riscv_insts_aext.sail riscv_insts_cext.sail riscv_insts_mext.sail riscv_insts_zicsr.sail riscv_insts_next.sail riscv_insts_hints.sail SAIL_DEFAULT_INST += riscv_insts_fext.sail riscv_insts_cfext.sail -ifeq ($(ARCH),RV64) SAIL_DEFAULT_INST += riscv_insts_dext.sail riscv_insts_cdext.sail -endif SAIL_DEFAULT_INST += riscv_insts_zkn.sail SAIL_DEFAULT_INST += riscv_insts_zks.sail |