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| author | Tim Hutt <timothy.hutt@codasip.com> | 2024-03-06 11:10:15 +0000 |
|---|---|---|
| committer | Bill McSpadden <bill@riscv.org> | 2024-03-25 09:16:00 -0500 |
| commit | d564b93310dd43f519325a418da056f78b1daef2 (patch) | |
| tree | f1e9d5a8a5d90b73f9932696dba5202f337f6a31 /model | |
| parent | 51b9732fe7cc85c0895039e181e522f4d846d3cd (diff) | |
| download | sail-riscv-d564b93310dd43f519325a418da056f78b1daef2.zip sail-riscv-d564b93310dd43f519325a418da056f78b1daef2.tar.gz sail-riscv-d564b93310dd43f519325a418da056f78b1daef2.tar.bz2 | |
Fix MEnvCall value
Fixes #294
Diffstat (limited to 'model')
| -rw-r--r-- | model/riscv_sys_regs.sail | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail index 2ab1771..4a5ab92 100644 --- a/model/riscv_sys_regs.sail +++ b/model/riscv_sys_regs.sail @@ -371,7 +371,7 @@ bitfield Medeleg : xlenbits = { SAMO_Page_Fault : 15, Load_Page_Fault : 13, Fetch_Page_Fault : 12, - MEnvCall : 10, + MEnvCall : 11, SEnvCall : 9, UEnvCall : 8, SAMO_Access_Fault : 7, |