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| author | Robert Norton <rmn30@cam.ac.uk> | 2019-07-01 13:51:14 +0100 |
|---|---|---|
| committer | Robert Norton <rmn30@cam.ac.uk> | 2019-07-01 13:51:14 +0100 |
| commit | 39584b6b1de69b05bcd6c167e63cfee3906f8bfc (patch) | |
| tree | 774bd3c03a4207c13e0ffb62fe16c06ff7fa98b0 /model | |
| parent | b3a9c7972d7c75b0e133f11def12c3c9f1a090f9 (diff) | |
| download | sail-riscv-39584b6b1de69b05bcd6c167e63cfee3906f8bfc.zip sail-riscv-39584b6b1de69b05bcd6c167e63cfee3906f8bfc.tar.gz sail-riscv-39584b6b1de69b05bcd6c167e63cfee3906f8bfc.tar.bz2 | |
Predicate another bit of tracing.
Diffstat (limited to 'model')
| -rw-r--r-- | model/riscv_platform.sail | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/model/riscv_platform.sail b/model/riscv_platform.sail index d440489..477731e 100644 --- a/model/riscv_platform.sail +++ b/model/riscv_platform.sail @@ -261,7 +261,8 @@ register htif_exit_code : bits(64) val htif_load : forall 'n, 'n > 0. (xlenbits, int('n)) -> MemoryOpResult(bits(8 * 'n)) effect {rreg} function htif_load(addr, width) = { - print_platform("htif[" ^ BitStr(addr) ^ "] -> " ^ BitStr(htif_tohost)); + if get_config_print_platform() then + print_platform("htif[" ^ BitStr(addr) ^ "] -> " ^ BitStr(htif_tohost)); /* FIXME: For now, only allow the expected access widths. */ if width == 8 & (addr == plat_htif_tohost()) then MemValue(sail_zero_extend(htif_tohost, 64)) /* FIXME: Redundant zero_extend currently required by Lem backend */ |