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authorTim Hutt <timothy.hutt@codasip.com>2024-05-14 14:51:57 +0100
committerAlasdair Armstrong <alasdair.armstrong@googlemail.com>2024-05-17 21:13:45 +0100
commit2259041cd6ef4d4e5acc6c8232e623e79476f408 (patch)
treef7cceff753bc624d6f995b07bd42a4b70cbcc28f /model
parent3688e5b0a3e594613c0dec4b9e8ba166a365cec8 (diff)
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Replace some bits(12)s with csreg
Very minor. Uses an existing type alias.
Diffstat (limited to 'model')
-rw-r--r--model/riscv_ext_regs.sail2
-rw-r--r--model/riscv_insts_zicsr.sail2
2 files changed, 2 insertions, 2 deletions
diff --git a/model/riscv_ext_regs.sail b/model/riscv_ext_regs.sail
index 28ed111..efe9bae 100644
--- a/model/riscv_ext_regs.sail
+++ b/model/riscv_ext_regs.sail
@@ -28,7 +28,7 @@ function ext_rvfi_init () = {
THIS(csrno, priv, isWrite) allows an extension to block access to csrno,
at Privilege level priv. It should return true if the access is allowed.
*/
-val ext_check_CSR : (bits(12), Privilege, bool) -> bool
+val ext_check_CSR : (csreg, Privilege, bool) -> bool
function ext_check_CSR (csrno, p, isWrite) = true
/*!
diff --git a/model/riscv_insts_zicsr.sail b/model/riscv_insts_zicsr.sail
index 7c52abd..f2980fb 100644
--- a/model/riscv_insts_zicsr.sail
+++ b/model/riscv_insts_zicsr.sail
@@ -10,7 +10,7 @@
/* This file specifies the instructions in the 'Zicsr' extension. */
/* ****************************************************************** */
-union clause ast = CSR : (bits(12), regidx, regidx, bool, csrop)
+union clause ast = CSR : (csreg, regidx, regidx, bool, csrop)
mapping encdec_csrop : csrop <-> bits(2) = {
CSRRW <-> 0b01,