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| author | Alasdair Armstrong <alasdair.armstrong@cl.cam.ac.uk> | 2019-11-01 16:24:58 +0000 |
|---|---|---|
| committer | Alasdair Armstrong <alasdair.armstrong@cl.cam.ac.uk> | 2019-11-01 16:24:58 +0000 |
| commit | 02d8312b88cfe5a97d6301295ec8b85a68c8f24d (patch) | |
| tree | 686c7c1ae05e943e84b8da4da820028aa1105c5e /model | |
| parent | 24fb6b4f43fb017c9855e5b9c9ccd241c09c5e86 (diff) | |
| download | sail-riscv-02d8312b88cfe5a97d6301295ec8b85a68c8f24d.zip sail-riscv-02d8312b88cfe5a97d6301295ec8b85a68c8f24d.tar.gz sail-riscv-02d8312b88cfe5a97d6301295ec8b85a68c8f24d.tar.bz2 | |
Fix up riscv_duopod and make self contained
Diffstat (limited to 'model')
| -rw-r--r-- | model/riscv_duopod.sail | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/model/riscv_duopod.sail b/model/riscv_duopod.sail index 395a332..b811824 100644 --- a/model/riscv_duopod.sail +++ b/model/riscv_duopod.sail @@ -1,4 +1,6 @@ -// This file depends on the xlen definitions in riscv_xlen.sail. + +$include "prelude.sail" +$include "riscv_xlen64.sail" type regbits = bits(5) @@ -23,7 +25,7 @@ function rX(r) = val wX : (regbits, xlenbits) -> unit effect {wreg} -function wX (r, v) = +function wX(r, v) = if r != 0b00000 then { Xs[unsigned(r)] = v; } |