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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-07-16 17:37:16 -0700 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-07-16 17:41:41 -0700 |
| commit | cc996651a3a756c862251e470dd21d9e19a4d420 (patch) | |
| tree | ad5a09b62e68aade733937ab5a3e00f3db9016a2 /model/riscv_vmem_common.sail | |
| parent | 39ed62d79e9f4ead6f52e755df9f9562e44696ac (diff) | |
| download | sail-riscv-cc996651a3a756c862251e470dd21d9e19a4d420.zip sail-riscv-cc996651a3a756c862251e470dd21d9e19a4d420.tar.gz sail-riscv-cc996651a3a756c862251e470dd21d9e19a4d420.tar.bz2 | |
Use reserved bits in PTEs for vmem extensions on RV64, as allowed by the spec. This is not possible for RV32, so pass zeros there.
Diffstat (limited to 'model/riscv_vmem_common.sail')
| -rw-r--r-- | model/riscv_vmem_common.sail | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/model/riscv_vmem_common.sail b/model/riscv_vmem_common.sail index f77366b..1a82d4c 100644 --- a/model/riscv_vmem_common.sail +++ b/model/riscv_vmem_common.sail @@ -106,6 +106,7 @@ bitfield SV39_Paddr : paddr64 = { } bitfield SV39_PTE : pte64 = { + Ext : 63 .. 54, PPNi : 53 .. 10, RSW : 9 .. 8, BITS : 7 .. 0 @@ -132,6 +133,7 @@ bitfield SV48_Paddr : paddr64 = { } bitfield SV48_PTE : pte48 = { + Ext : 63 .. 54, PPNi : 53 .. 10, RSW : 9 .. 8, BITS : 7 .. 0 |