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| author | Tim Hutt <timothy.hutt@codasip.com> | 2024-03-06 11:27:29 +0000 |
|---|---|---|
| committer | Bill McSpadden <bill@riscv.org> | 2024-03-24 19:46:11 -0500 |
| commit | fd21acc266716d9bd04fc96d60fed375005d6888 (patch) | |
| tree | aa57dff37f32a682603a510d17332e18bece7c0f /model/riscv_insts_rmem.sail | |
| parent | c287c34df944647fcfd1923e37f4d97466f264bd (diff) | |
| download | sail-riscv-fd21acc266716d9bd04fc96d60fed375005d6888.zip sail-riscv-fd21acc266716d9bd04fc96d60fed375005d6888.tar.gz sail-riscv-fd21acc266716d9bd04fc96d60fed375005d6888.tar.bz2 | |
Add RV32 restriction for compressed shift instructions
The restriction was present for `C.SLLI` but was missing for `C.SRLI` and `C.SRAI`.
The format is copied from `C.SLLI`.
Fixes #356
Diffstat (limited to 'model/riscv_insts_rmem.sail')
0 files changed, 0 insertions, 0 deletions