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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-11-12 17:44:10 -0800 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-11-12 17:44:10 -0800 |
| commit | 9c9974a6ef7481408f64fbc90c56dbeabcdf6641 (patch) | |
| tree | 010975f2b0f6f5ea77f5888194d9820ba1ed2522 /model/riscv_flen_D.sail | |
| parent | 539450b0b120f3b59667d2c0f2f5a3771a23f03b (diff) | |
| download | sail-riscv-9c9974a6ef7481408f64fbc90c56dbeabcdf6641.zip sail-riscv-9c9974a6ef7481408f64fbc90c56dbeabcdf6641.tar.gz sail-riscv-9c9974a6ef7481408f64fbc90c56dbeabcdf6641.tar.bz2 | |
Fix a typo in setting flenbits.
Diffstat (limited to 'model/riscv_flen_D.sail')
| -rw-r--r-- | model/riscv_flen_D.sail | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/model/riscv_flen_D.sail b/model/riscv_flen_D.sail index f093c9f..eabd613 100644 --- a/model/riscv_flen_D.sail +++ b/model/riscv_flen_D.sail @@ -2,4 +2,4 @@ type flen : Int = 64 type flen_bytes : Int = 8 -type flenbits = bits(xlen) +type flenbits = bits(flen) |