From 9c9974a6ef7481408f64fbc90c56dbeabcdf6641 Mon Sep 17 00:00:00 2001
From: Prashanth Mundkur <prashanth.mundkur@gmail.com>
Date: Tue, 12 Nov 2019 17:44:10 -0800
Subject: Fix a typo in setting flenbits.

---
 model/riscv_flen_D.sail | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'model/riscv_flen_D.sail')

diff --git a/model/riscv_flen_D.sail b/model/riscv_flen_D.sail
index f093c9f..eabd613 100644
--- a/model/riscv_flen_D.sail
+++ b/model/riscv_flen_D.sail
@@ -2,4 +2,4 @@
 
 type flen       : Int = 64
 type flen_bytes : Int = 8
-type flenbits         = bits(xlen)
+type flenbits         = bits(flen)
-- 
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