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authorTim Hutt <timothy.hutt@codasip.com>2023-09-23 19:57:38 +0100
committerBill McSpadden <bill@riscv.org>2023-10-11 20:50:13 -0500
commit51a6c967fb320c2d47a3630b1f392e54eb69c3d7 (patch)
treecd864017e11911f4e86c32e7a437993a9ce05a58 /c_emulator/riscv_sim.c
parent532714a6c71b47a91176eb90fef3b3b049c52fce (diff)
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Implement menvcfg
This implements the m/senvcfg(h) CSRs. This CSR is used to enable/disable extensions and behaviours for lower privilege modes. Currently the only implemented bit is FIOM which affects how fences work. It also affects how atomic memory accesses work in non-cacheable regions, but the model does not currently support PMAs so that can't easily be implemented.
Diffstat (limited to 'c_emulator/riscv_sim.c')
-rw-r--r--c_emulator/riscv_sim.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/c_emulator/riscv_sim.c b/c_emulator/riscv_sim.c
index 8f7f9e1..d841c6d 100644
--- a/c_emulator/riscv_sim.c
+++ b/c_emulator/riscv_sim.c
@@ -50,6 +50,7 @@ const char *RV32ISA = "RV32IMAC";
#define CSR_MIP 0x344
#define OPT_TRACE_OUTPUT 1000
+#define OPT_ENABLE_FIOM 1001
static bool do_dump_dts = false;
static bool do_show_times = false;
@@ -140,6 +141,7 @@ static struct option options[] = {
{"trace-output", required_argument, 0, OPT_TRACE_OUTPUT},
{"inst-limit", required_argument, 0, 'l' },
{"enable-zfinx", no_argument, 0, 'x' },
+ {"enable-fiom", no_argument, 0, OPT_ENABLE_FIOM },
#ifdef SAILCOV
{"sailcov-file", required_argument, 0, 'c' },
#endif
@@ -302,6 +304,11 @@ static int process_args(int argc, char **argv)
fprintf(stderr, "enabling storing illegal instruction bits in mtval.\n");
rv_mtval_has_illegal_inst_bits = true;
break;
+ case OPT_ENABLE_FIOM:
+ fprintf(stderr,
+ "enabling FIOM (Fence of I/O implies Memory) bit in menvcfg.\n");
+ rv_enable_fiom = true;
+ break;
case 's':
do_dump_dts = true;
break;