Implement menvcfg

This implements the m/senvcfg(h) CSRs. This CSR is used to enable/disable extensions and behaviours for lower privilege modes. Currently the only implemented bit is FIOM which affects how fences work.

It also affects how atomic memory accesses work in non-cacheable regions, but the model does not currently support PMAs so that can't easily be implemented.

5 files changed, 15 insertions, 0 deletions

diff --git a/c_emulator/riscv_platform.c b/c_emulator/riscv_platform.c
index 917a36a..52e050a 100644
--- a/c_emulator/riscv_platform.c
+++ b/c_emulator/riscv_platform.c
@@ -37,6 +37,11 @@ bool sys_enable_zfinx(unit u)
   return rv_enable_zfinx;
 }
 
+bool sys_enable_fiom(unit u)
+{
+  return rv_enable_fiom;
+}
+
 bool sys_enable_writable_misa(unit u)
 {
   return rv_enable_writable_misa;
diff --git a/c_emulator/riscv_platform.h b/c_emulator/riscv_platform.h
index aec59d0..8dadbd5 100644
--- a/c_emulator/riscv_platform.h
+++ b/c_emulator/riscv_platform.h
@@ -6,6 +6,7 @@ bool sys_enable_next(unit);
 bool sys_enable_fdext(unit);
 bool sys_enable_zfinx(unit);
 bool sys_enable_writable_misa(unit);
+bool sys_enable_fiom(unit);
 
 bool plat_enable_dirty_update(unit);
 bool plat_enable_misaligned_access(unit);
diff --git a/c_emulator/riscv_platform_impl.c b/c_emulator/riscv_platform_impl.c
index 148c72b..805dd3c 100644
--- a/c_emulator/riscv_platform_impl.c
+++ b/c_emulator/riscv_platform_impl.c
@@ -13,6 +13,7 @@ bool rv_enable_fdext = true;
 bool rv_enable_dirty_update = false;
 bool rv_enable_misaligned = false;
 bool rv_mtval_has_illegal_inst_bits = false;
+bool rv_enable_fiom = true;
 
 uint64_t rv_ram_base = UINT64_C(0x80000000);
 uint64_t rv_ram_size = UINT64_C(0x4000000);
diff --git a/c_emulator/riscv_platform_impl.h b/c_emulator/riscv_platform_impl.h
index aa8d391..a2c758f 100644
--- a/c_emulator/riscv_platform_impl.h
+++ b/c_emulator/riscv_platform_impl.h
@@ -17,6 +17,7 @@ extern bool rv_enable_writable_misa;
 extern bool rv_enable_dirty_update;
 extern bool rv_enable_misaligned;
 extern bool rv_mtval_has_illegal_inst_bits;
+extern bool rv_enable_fiom;
 
 extern uint64_t rv_ram_base;
 extern uint64_t rv_ram_size;
diff --git a/c_emulator/riscv_sim.c b/c_emulator/riscv_sim.c
index 8f7f9e1..d841c6d 100644
--- a/c_emulator/riscv_sim.c
+++ b/c_emulator/riscv_sim.c
@@ -50,6 +50,7 @@ const char *RV32ISA = "RV32IMAC";
 #define CSR_MIP 0x344
 
 #define OPT_TRACE_OUTPUT 1000
+#define OPT_ENABLE_FIOM 1001
 
 static bool do_dump_dts = false;
 static bool do_show_times = false;
@@ -140,6 +141,7 @@ static struct option options[] = {
     {"trace-output",                required_argument, 0, OPT_TRACE_OUTPUT},
     {"inst-limit",                  required_argument, 0, 'l'             },
     {"enable-zfinx",                no_argument,       0, 'x'             },
+    {"enable-fiom",                 no_argument,       0, OPT_ENABLE_FIOM },
 #ifdef SAILCOV
     {"sailcov-file",                required_argument, 0, 'c'             },
 #endif
@@ -302,6 +304,11 @@ static int process_args(int argc, char **argv)
       fprintf(stderr, "enabling storing illegal instruction bits in mtval.\n");
       rv_mtval_has_illegal_inst_bits = true;
       break;
+    case OPT_ENABLE_FIOM:
+      fprintf(stderr,
+              "enabling FIOM (Fence of I/O implies Memory) bit in menvcfg.\n");
+      rv_enable_fiom = true;
+      break;
     case 's':
       do_dump_dts = true;
       break;