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| author | guan jian <148229859+rez5427@users.noreply.github.com> | 2024-10-19 21:50:04 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-10-19 06:50:04 -0700 |
| commit | 2a2a950cac0c52ecbfacfeeecde47b2570b33994 (patch) | |
| tree | 35f5a96f50ca3ab815d14bbde4dcb62e1248c807 /c_emulator/riscv_sim.c | |
| parent | 81b0bf96e1fd89d453b140fe3a7640fe85398ecb (diff) | |
| download | sail-riscv-master.zip sail-riscv-master.tar.gz sail-riscv-master.tar.bz2 | |
Remove the registers which don't exist in the ISA and were unnecessary. They have been replaced by sys_ callbacks which are not currently connected to CLI arguments, but we can hook them up to the new config system when it is available.
Co-authored-by: Yui5427 <785369607@qq.com>
Diffstat (limited to 'c_emulator/riscv_sim.c')
0 files changed, 0 insertions, 0 deletions