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authorMartin Berger <contact@martinfriedrichberger.net>2024-04-29 23:26:40 +0100
committerBill McSpadden <bill@riscv.org>2024-05-07 19:56:04 -0500
commit34e43b27fa47472cf0abd035f49114734a283d29 (patch)
tree30203c7389fb4167a875e62989f013fd8d7e1b14 /c_emulator/riscv_platform.c
parentc5ee87dfcc862a69ccad6e560423da4bb0e99dd6 (diff)
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Add Svinval extension.
These changes add the "Svinval" Standard Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0 to the sail-riscv model. This extension defines five new instructions: SINVAL.VMA, SFENCE.W.INVAL, SFENCE.INVAL.IR, HINVAL.VVMA, HINVAL.GVMA. HINVAL.VVMA & HINVAL.GVMA are omitted since they build on the Hypervisor Extension which is yet to be included in the model. SFENCE.W.INVAL & SFENCE.INVAL.IR are treated as nops pending integration of the coherency model (rmem) with sail. The specification says that SINVAL.VMA behaves just as SFENCE.VMA, except there are additional ordering constraints with respect to the new SFENCE.W.INVAL & SFENCE.INVAL.IR instructions. Since these are nops, we can treat SINVAL.VMA as if it were SFENCE.VMA.
Diffstat (limited to 'c_emulator/riscv_platform.c')
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