sail-riscv.git - Unnamed repository; edit this file 'description' to name the repository.

Branch	Commit message	Author	Age
billmcspadden-riscv	Add a new recipe to run the Sail tests manually via GH Actions (#229)	Rafael Sene	16 months
fix-signature-granularity	Merge pull request #244 from billmcspadden-riscv/fix-signature-granularity	Philipp Tomsich	15 months
haveSmepmp_billmcspadden	removed whitespace	William McSpaddden	9 weeks
hpm_events_billmcspadden	missed a file	William McSpaddden	13 months
hpm_events_billmcspadden__sail_error_message_is_terse	demonstrates terse error message. error is at model/riscv_hpmevents.sail lin...	William McSpaddden	13 months
master	Merge pull request #498 from Timmmm/user/timh/bigger_tlb_2	Bill McSpadden	37 hours
new_test_2	added newline at end of file. bah.	William McSpaddden	2 months
new_test_3	testing out git subtree	William McSpaddden	8 weeks
update-copyright-headers	apply_headers: regenerate copyright headers	Philipp Tomsich	14 months
vector-dev	RISC-V Vector Extension Support	Xinlai Wan	9 months
[...]

Tag	Download	Author	Age
0.5	sail-riscv-0.5.zip sail-riscv-0.5.tar.gz sail-riscv-0.5.tar.bz2	Thibaut Pérami	4 years
0.4	sail-riscv-0.4.zip sail-riscv-0.4.tar.gz sail-riscv-0.4.tar.bz2	Robert Norton	5 years
0.3	sail-riscv-0.3.zip sail-riscv-0.3.tar.gz sail-riscv-0.3.tar.bz2	Robert Norton	5 years
0.2	sail-riscv-0.2.zip sail-riscv-0.2.tar.gz sail-riscv-0.2.tar.bz2	Robert Norton	5 years
0.1	sail-riscv-0.1.zip sail-riscv-0.1.tar.gz sail-riscv-0.1.tar.bz2	Robert Norton	5 years

Age	Commit message	Author	Files	Lines
2020-09-18	Handle empty predecessor or successor sets in FENCE as no-ops.fence_noops	Prashanth Mundkur	1	-0/+4
2020-09-05	Update status and docs for hints.	Prashanth Mundkur	2	-4/+2
2020-09-04	Handle hints explicitly in order to not trap on them.	Prashanth Mundkur	2	-1/+159
2020-09-03	Add the mstatush CSR for RV32, and hardwire the MBE and SBE fields to 0.	Prashanth Mundkur	3	-0/+26
2020-08-27	Merge pull request #66 from scottj97/mcountinhibit	Prashanth Mundkur	3	-1/+4
2020-08-25	Implement mcountinhibit IR bit to squash minstret increment	Scott Johnson	1	-1/+2
2020-08-25	Allow CSR read/write to mcountinhibit	Scott Johnson	1	-0/+1
2020-08-25	Add missing disassembler mapping for mcountinhibit CSR	Scott Johnson	1	-0/+1
2020-08-20	Fix conditions CSR definedness. Fixes #65.	Prashanth Mundkur	1	-11/+11
2020-08-04	Add a line pointing to the instructions for latex inclusion in the prose spec...	Prashanth Mundkur	1	-0/+1
[...]