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2018-11-19Disable the DM when OpenOCD exits.deinitTim Newsome1-0/+3
2018-11-19From upstream (#331)Tim Newsome25-599/+3632
2018-11-12examine() should leave halted harts halted (#327)Tim Newsome1-6/+5
2018-11-07Doxygen style, too. (#325)Tim Newsome2-3/+3
2018-11-05Conform to OpenOCD style. (#323)Tim Newsome1-1/+1
2018-11-05Install patchutils for the build. (#321)Tim Newsome1-3/+2
2018-11-05Complete single step before returning. (#319)Tim Newsome1-1/+1
2018-11-05FIX(src/target/riscv/riscv.c): riscv_add_breakpoint: RVC: invalid 32bit trans...Pavel S. Smirnov1-10/+19
2018-11-02Fix 0.11 memory leak. (#318)Tim Newsome1-3/+3
2018-10-30Old fixes from June (#311)Carsten Gosvig3-36/+57
2018-10-24Revert "Don't report exact watchpoint to gdb. (#300)" (#304)Tim Newsome1-5/+1
2018-10-19Merge pull request #308 from riscv/eclipse_memory_readCarsten Gosvig1-44/+81
2018-10-19Moved comment and added initial buffer clearingv20180928eclipse_memory_readcgsfv1-3/+5
2018-10-18dmi_scan() allocate bytes depending on abits value (#307)Tim Newsome1-3/+7
2018-10-18Fix segfault in riscv_deinit_target(). (#306)Tim Newsome1-6/+11
2018-09-17Corrected wrong C syntaxcgsfv1-1/+1
2018-09-17Read memory words individually if burst read failscgsfv1-44/+79
2018-09-06Don't report exact watchpoint to gdb. (#300)Tim Newsome1-1/+5
2018-08-31More style fixesRyan Macdonald1-1/+1
2018-08-31Style fixesRyan Macdonald1-5/+4
2018-08-31Add pass message for SBA and compliance testsRyan Macdonald1-14/+42
2018-08-31Merge remote-tracking branch 'origin/riscv' into sba_testssba_testsMegan Wachs5-2/+488
2018-08-30riscv-compliance: fix comment typoriscv-complianceMegan Wachs1-1/+1
2018-08-30riscv-compliance: fix whitespaceMegan Wachs1-25/+25
2018-08-30riscv-compliance: incorporate review feedbackMegan Wachs1-123/+108
2018-08-29Fix typo.Tim Newsome1-1/+1
2018-08-29Fix strange merge.Tim Newsome1-2/+0
2018-08-29Merge branch 'riscv' into sba_testsTim Newsome58-2272/+6499
2018-08-29Merge remote-tracking branch 'origin/riscv' into riscv-compliance-rebaseMegan Wachs36-1143/+3205
2018-08-29Add command to expose custom registers (#293)Tim Newsome3-42/+140
2018-08-27Handle hardware watchpoints hit by RV32 loads and stores (#291)craigblackmore3-1/+86
2018-08-23Switch active rtos thread on any hart halt. (#290)Dmitry Ryzhov1-0/+1
2018-08-20From upstream (#286)Tim Newsome23-116/+396
2018-08-20Remove unused variable. (#284)Tim Newsome1-2/+0
2018-08-06Fix target not halting when GDB jumps to a hardware breakpoint (#283)craigblackmore1-12/+0
2018-07-18Mimic openrisc Makefile structureTim Newsome2-10/+20
2018-07-17Merge pull request #279 from riscv/work_areaTim Newsome3-52/+40
2018-07-16Use work area instead of riscv-specific configTim Newsome3-52/+40
2018-06-20Explain why reg_cache_values isn't per-hart.Tim Newsome1-1/+3
2018-06-12target/riscv: fix trailing spacesLiviu Ionescu1-10/+10
2018-06-12target/riscv: explain why `arm` commands are usedLiviu Ionescu1-0/+13
2018-06-12target/riscv: add semihosting supportLiviu Ionescu5-0/+257
2018-06-11Merge branch 'master' into from_upstreamTim Newsome15-746/+2021
2018-06-06Update debug defines to match specTim Newsome3-300/+324
2018-06-06target/target.c: free semihosting memberLiviu Ionescu1-0/+3
2018-06-05target/cortex_m: constify some variablesChristopher Head1-4/+4
2018-06-04breakpoints: simplify the test to find a breakpointAntonio Borneo1-5/+2
2018-06-04target: fix syntax in help messageAntonio Borneo1-3/+1
2018-06-04target: aarch64: Adding mcr, mrc 32-bit coprocesor read/write supportKamal Dasu1-0/+153
2018-06-04Rework/update ARM semihostingLiviu Ionescu11-734/+1858
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