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2018-08-31Merge remote-tracking branch 'origin/riscv' into sba_testssba_testsMegan Wachs5-2/+488
2018-08-30riscv-compliance: fix comment typoriscv-complianceMegan Wachs1-1/+1
2018-08-30riscv-compliance: fix whitespaceMegan Wachs1-25/+25
2018-08-30riscv-compliance: incorporate review feedbackMegan Wachs1-123/+108
2018-08-29Fix typo.Tim Newsome1-1/+1
2018-08-29Fix strange merge.Tim Newsome1-2/+0
2018-08-29Merge branch 'riscv' into sba_testsTim Newsome58-2272/+6499
2018-08-29Merge remote-tracking branch 'origin/riscv' into riscv-compliance-rebaseMegan Wachs36-1143/+3205
2018-08-29Add command to expose custom registers (#293)Tim Newsome3-42/+140
2018-08-27Handle hardware watchpoints hit by RV32 loads and stores (#291)craigblackmore3-1/+86
2018-08-23Switch active rtos thread on any hart halt. (#290)Dmitry Ryzhov1-0/+1
2018-08-20From upstream (#286)Tim Newsome23-116/+396
2018-08-20Remove unused variable. (#284)Tim Newsome1-2/+0
2018-08-06Fix target not halting when GDB jumps to a hardware breakpoint (#283)craigblackmore1-12/+0
2018-07-18Mimic openrisc Makefile structureTim Newsome2-10/+20
2018-07-17Merge pull request #279 from riscv/work_areaTim Newsome3-52/+40
2018-07-16Use work area instead of riscv-specific configTim Newsome3-52/+40
2018-06-20Explain why reg_cache_values isn't per-hart.Tim Newsome1-1/+3
2018-06-12target/riscv: fix trailing spacesLiviu Ionescu1-10/+10
2018-06-12target/riscv: explain why `arm` commands are usedLiviu Ionescu1-0/+13
2018-06-12target/riscv: add semihosting supportLiviu Ionescu5-0/+257
2018-06-11Merge branch 'master' into from_upstreamTim Newsome15-746/+2021
2018-06-06Update debug defines to match specTim Newsome3-300/+324
2018-06-06target/target.c: free semihosting memberLiviu Ionescu1-0/+3
2018-06-05target/cortex_m: constify some variablesChristopher Head1-4/+4
2018-06-04breakpoints: simplify the test to find a breakpointAntonio Borneo1-5/+2
2018-06-04target: fix syntax in help messageAntonio Borneo1-3/+1
2018-06-04target: aarch64: Adding mcr, mrc 32-bit coprocesor read/write supportKamal Dasu1-0/+153
2018-06-04Rework/update ARM semihostingLiviu Ionescu11-734/+1858
2018-05-30Merge branch 'master' into from_upstreamTim Newsome2-3/+5
2018-05-30Fix warnings exposed by GCC8Paul Fertser2-3/+5
2018-05-25Merge pull request #261 from riscv/trigger_enumv20180629Tim Newsome3-5/+19
2018-05-22Merge remote-tracking branch 'origin/trigger_enum' into riscv-complianceriscv-compliance-devMegan Wachs3-5/+19
2018-05-22Merge remote-tracking branch 'origin/riscv' into riscv-complianceMegan Wachs24-152/+303
2018-05-22Merge pull request #257 from riscv/commentTim Newsome2-0/+8
2018-05-22Delay trigger enumeration until it's required.Tim Newsome3-5/+19
2018-05-22Fix posible null deref in get_target_typeDan Robertson1-3/+10
2018-05-17Review feedback.Tim Newsome1-1/+1
2018-05-17Comment riscv_set_register, register_write_directTim Newsome2-0/+8
2018-05-17Merge pull request #251 from riscv/from_upstreamTim Newsome23-149/+285
2018-05-16Merge remote-tracking branch 'origin/reset-unexpected-check' into riscv-compl...Megan Wachs1-8/+0
2018-05-16riscv: remove unexpected check during resetMegan Wachs1-8/+0
2018-05-14Merge remote-tracking branch 'origin/riscv' into riscv-complianceMegan Wachs3-103/+222
2018-05-08blank_check_memory prototype has changed.Tim Newsome1-17/+0
2018-05-08arm_dpm: flush both scratch registers (R0 and R1)Philipp Tomsich1-5/+7
2018-05-08target/cortex_m: allow setting the type of a breakpointTomas Vanek2-29/+1
2018-05-08armv8: valgrind memleak fixesMatthias Welwarsky5-7/+70
2018-05-08target armv7m: multi-block erase checkTomas Vanek1-39/+95
2018-05-08target, flash: prepare infrastructure for multi-block blank checkTomas Vanek10-33/+53
2018-05-08target: free target SMP list on shutdownMatthias Welwarsky1-0/+12
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