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2022-07-23openocd: src/target: replace the GPL-2.0-or-later license tagAntonio Borneo1-13/+2
Replace the FSF boilerplate with the SPDX tag. The SPDX tag on files *.c is incorrect, as it should use the C99 single line comment using '//'. But current checkpatch doesn't allow C99 comments, so keep using standard C comments, by now. Change-Id: I255ad17235ff1e01bf0aa4deed4d944e1d693ddb Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7071 Tested-by: jenkins
2020-03-12target/cortex_a: add hypervisor modeAntonio Borneo1-1/+1
Hypervisor mode is present only if the optional virtualization extensions are available. Moreover, virtualization extensions require that also security extensions are implemented. Add the required infrastructure for the shadowed registers in hypervisor mode. Make monitor shadowed registers visible in hypervisor mode too. Make hypervisor shadowed registers visible in hypervisor mode only. Check during cortex_a examine if virtualization extensions are present and then conditionally enable the visibility of both hypervisor and monitor modes shadowed registers. Change-Id: I81dbb1ee8baf4c9f1a2226b77c10c8a2a7b34871 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5261 Tested-by: jenkins
2016-05-24Make #include guard naming consistentMarc Schink1-3/+3
Change-Id: Ie13e8af0bb74ed290f811dcad64ad06c9d8cb4fa Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/2956 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-24Remove FSF address from GPL noticesMarc Schink1-3/+1
Also make GPL notices consistent according to: https://www.gnu.org/licenses/gpl-howto.html Change-Id: I84c9df40a774958a7ed91460c5d931cfab9f45ba Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/3488 Tested-by: jenkins Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-06-05update files to correct FSF addressSpencer Oliver1-1/+1
Change-Id: I429f7fd51f77b0e7c86d7a7f110ca31afd76c173 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1426 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2012-02-06build: cleanup src/target directorySpencer Oliver1-1/+2
Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2009-12-07ARM: use <target/arm.h> not armv4_5.hDavid Brownell1-168/+3
Move most declarations in <target/armv4_5.h> to <target/arm.h> and update users. What's left in the older file is stuff that I think should be removed ... the old register cache access stuff, which makes it awkward to support microcontroller profile (Cortex-M) cores. The armv4_5_run_algorithm() declaration was moved too, even though it's not yet as generic as it probably ought to be. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-07ARM: rename some generic routinesDavid Brownell1-3/+3
Rename some (mostly) generic ARM functions: armv4_5_arch_state() --> arm_arch_state() armv4_5_get_gdb_reg_list() --> arm_get_gdb_reg_list() armv4_5_init_arch_info() --> arm_init_arch_info() Cores using the microcontroller profile may want a different arch_state() routine though. (Also fix strange indentation in arm_arch_state: use tabs only! And update a call to it, removing assignment-in-conditional.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-07ARM: move opcode macros to <target/arm_opcodes.h>David Brownell1-167/+0
Move the ARM opcode macros from <target/armv4_5.h>, and a few Thumb2 ones from <target/armv7m.h>, to more appropriate homes in a new <target/arm_opcodes.h> file. Removed duplicate opcodes from that v7m/Thumb2 set. Protected a few macro argument references by adding missing parentheses. Tightening up some of the line lengths turned up a curious artifact: the macros for the Thumb opcodes are all 32 bits wide, not 16 bits. There's currently no explanation for why it's done that way... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-07ARM: remove mrc_opcode(), use MRC() or MCR()David Brownell1-12/+0
Get rid of mrc_opcode() in favor of ARMV4_5_MRC() or, where arm*20t should have used it, ARMV4_5_MCR() instead. Basically, *writing* coprocessor registers shouldn't have used the *read* opcode ... and both should stick to standard opcode constructors, not rearranging parameter sequence any more than already needed. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-04ARM: doc updates for main headerDavid Brownell1-3/+11
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-04ARM: rename armv4_5_build_reg_cache() as arm_*()David Brownell1-2/+1
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-04ARM: rename armv4_5_algorithm as arm_algorithmDavid Brownell1-1/+1
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-04ARM: misc generic cleanupDavid Brownell1-9/+17
Remove an undesirable use of the CPSR symbol ... it needs to vanish. Flag mode-to-number stuff as obsolete; say why ... should also vanish. Get rid of no-longer-used mode and state typedefs. Comment a few of the implicit ties to "classic ARM". Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-04ARM: ARMV4_5_COMMON_MAGIC --> ARM_COMMON_MAGICDavid Brownell1-2/+2
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-04ARM: switch target_to_armv4_5() to target_to_arm()David Brownell1-2/+0
And remove that old symbol. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-04ARM: rename armv4_5_state_* as arm_state_*David Brownell1-5/+5
And make arm_state_strings[] be const. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-04ARM: rename armv4_5_mode_* AS arm_mode_*David Brownell1-11/+11
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-04ARM: rename ARMV4_5_MODE_* as ARM_MODE_*David Brownell1-9/+9
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-04ARM: rename ARMV4_5_STATE_* as ARM_STATE_*David Brownell1-3/+3
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-04ARM: remove semihosting globalsDavid Brownell1-0/+6
Store a flag and errno in in "struct arm". Have "poll" output report when semihosting is active. Shrink some of the affected lines. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-03change #include "target.h" to <target/target.h>Zachary T Welch1-1/+1
Changes from the flat namespace to heirarchical one. Instead of writing: #include "target.h" the following form should be used. #include <target/target.h> The exception is from .c files in the same directory.
2009-12-03change #include "command.h" to <helper/command.h>Zachary T Welch1-1/+1
Changes from the flat namespace to heirarchical one. Instead of writing: #include "command.h" the following form should be used. #include <helper/command.h> The exception is from .c files in the same directory.
2009-12-01target: "mcr" and "mrc" are ARM-specificDavid Brownell1-0/+15
Switch "mrc" and "mcr" commands to be toplevel ARM operations, as they should initially have been. Correct the usage message for both commands: it matches ARM documentation (as one wants!) instead of reordering them to match the funky mrc() and mcr() method usage (sigh). For Cortex-A8: restore a line that got accidentally dropped, so the secure monitor mode shadow registers will show again. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-24remove target_type register_command callbackZachary T Welch1-1/+4
Uses chaining of command_registration structures to eliminate all target_type register_callback routines. Exports the command_handler registration arrays for those target types that are used by others.
2009-11-24ARM: new DPM interfaceDavid Brownell1-0/+6
First version of interface for sharing code between ARMv6 and ARMv7a debug modules ... now the architecture includes debug support. (Not the same as for the trimmed-down v7m or v6m though!) This is a first version of an interface that will let the ARM11 and Cortex-A8 support share code, features, and bugfixes. Based on existing code from both of those cores. The ARM v7-AR architecture specification calls this commonality the "Debug Programmer's Model (DPM)", which seemed to be an appropriate acronym -- a TLA even! -- for use in our code. Made it so. :) The initial scope of this just supports register access, and is geared towards supporting top level "struct arm" mechanisms. Later, things like breakpoint and watchpoint support should be included. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-22ARM: remove 'armv4_5_common_s' migration #defineDavid Brownell1-3/+0
Finish migrating from the old symbol to the new one. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-22ARM: define two register utilitiesDavid Brownell1-0/+8
Define arm_reg_current() ... returning handle to a given register, and encapsulating the current mode's register shadowing. It's got one current use, for reporting the current register set to GDB. This will let later patches clean up much ARMV4_5_CORE_REG_MODE() nastiness, saving a bit of code. Define and use arm_set_cpsr() ... initially it updates the cached CPSR and sets up state used by arm_reg_current(), plus any SPSR handle. (Later: can also set up for T and J bits.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-22ARM: simplify CPSR handlingDavid Brownell1-11/+5
Stash a pointer to the CPSR in the "struct arm", to help get rid of the (common) references to its index in the register cache. This removes almost all references to CPSR offsets outside of the toplevel ARM code ... except a pair related to the current ARM11 "simulator" logic (which should be removable soonish). This is a net minor code shrink of a few hundred bytes of object code, and also makes the code more readable. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-20ARM: pass 'struct reg *' to register r/w routinesDavid Brownell1-3/+3
Implementations need to access the register struct they modify; make it easier and less error-prone to identify the instance. (This removes over 10% of the ARMV4_5_CORE_REG_MODE nastiness...) Plus some minor fixes noted when making these updates: ARM7/ARM9 accessor methods should be static; don't leave CPSR wrongly marked "dirty"; note significant XScale omissions in register handling; and have armv4_5_build_reg_cache() record its result. Rename "struct armv4_5_core_reg" as "struct arm_reg"; it's used for more than those older architecture generations. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-19target: create/use register_cache_invalidate()David Brownell1-2/+0
Create a generic register_cache_invalidate(), and use it to replace three all-but-identical core-specific routines: - armv4_5_invalidate_core_regs() - armv7m_invalidate_core_regs - mips32_invalidate_core_regs() too. Make cache->num_regs be unsigned, avoiding various errors. Net code shrink and simplification. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-19ARM: remove per-register mallocDavid Brownell1-0/+1
Just pre-allocate memory for the cached register value. Shrinks heap overhead; increases locality-of-reference. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-19ARMv7-A: use standard ARM core statesDavid Brownell1-0/+1
We don't want an ARMv7-specific core state enumeration just to add ThumbEE state. Update the generic stuff to handle that, and replace the V7-specific bits with it. For Cortex-A8: on debug entry, check both the T and J bits instead of just the T bit. When the J bit is set, set the right state and warn appropriately. (And while we're at it, move the generic arm struct to the front of the v7a structure, for somewhat better code generation.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-18ARM: setup "secure monitor mode" shadow regsDavid Brownell1-2/+3
Teach the "armv4_5" register code to understand about the secure monitor mode: - Add the other three shadowed registers to the arrays - Support another internal mode number (sigh) in mappings - Catch malloc/calloc failures building that register cache This should kick in for Cortex-A8 and ARM1176. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-18ARM: add "core_type" field to "struct arm"David Brownell1-1/+9
It's used to flag cores with the "TrustZone" extension, and is used in subsequent patches to set up support for the registers shadowed by its new secure monitor mode. The ARM1176 and Cortex-A8 both support this new mode. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-17ARM: add is_arm_mode()David Brownell1-3/+3
Add a new is_arm_mode() predicate, and use it to replace almost all calls to current armv4_5_mode_to_number(). Eventually those internal mode numbers should vanish... along with their siblings in the armv7a.c file. Remove a handful of superfluous checks ... e.g. the mode number was just initialized, or (debug entry methods) already validated. Move one of the macros using internal mode numbers into the only file which uses that macro. Make the tables manipulated with those numbers be read-only and, where possible, static so they're not confused with part of the generic ARM interface. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-17ARM: add arm_mode_name()David Brownell1-2/+2
Add and use arm_mode_name() to map from PSR bits to user meaningful names. It uses a new table which, later, can be used to hold other mode-coupled data. Add definitions for the "Secure Monitor" mode, as seen on some ARM11 cores (like ARM1176) and on Cortex-A8. The previous mode name scheme didn't understand that mode. Remove the old mechanism ... there were two copies, caused by Cortex-A8 needing to add "Secure Monitor" mode support. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-17ARM: only use one set of dummy FPA registersDavid Brownell1-0/+2
All ARM cores need to provide obsolete FPA registers in their GDB register dumps. (Even though cores with floating point support now generally use some version of VFP...) Clean up that support a bit by sharing the same dummy registers, and removing the duplicate copies. Eventually we shouldn't need to export those dummies. (This makes the ARMv7-M support include the armv4_5 header, and cleans up related #includes, but doesn't yet use anything from there except those dummies.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-16target: don't include "log.h" from "armv4_5.h"David Brownell1-1/+0
No point in multiple includes, and that file doesn't use its functions any more. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-16ARM: move mode functions out of headerDavid Brownell1-38/+4
They're really too big to inline, at least for code that's not in any performance-critical loops. Also move the associated string table to the rodata section. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-16target: less implicit inclusion of "etm.h"David Brownell1-1/+1
Don't include it in more headers than necessary; just use it in the few files that actually need it. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-16target: no implicit #includes of "register.h"David Brownell1-1/+0
Same deal: "register.h" got needlessly included all over the place because of being in a few widely included headers. So take it out of the header files which included it, and put it in files which use it ... reduce needless interdependencies. Also, don't need that extra "types.h" inclusion. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-16target: less implicit inclusion of "command.h"David Brownell1-1/+0
Lots of files still include it, often through needless duplicate inclusion of "log.h"; sigh. This cleans up the inclusion graph a bunch, so there are fewer inclusion paths, but it doesn't change much otherwise. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-15ARM: memory utils aren't ARM7/ARM9 dependentDavid Brownell1-3/+6
The arm7_9_checksum_memory() and arm7_9_blank_check_memory() routines are not actually specific to the ARM7 and ARM9 core generations ... they can work for any core which can run algorithms using basic ARM (not Thumb) instructions. Rename them; move the declarations to a more generic site; likewise move the code (and tidy it a bit in the process). NOTE: the blank_check() method falsely returned a success status (0) on one error path, when the algorithm failed. Fixed this bug. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-13command_context_t -> struct command_contextZachary T Welch1-1/+1
Remove misleading typedef and redundant suffix from struct command_context.
2009-11-13target_t -> struct targetZachary T Welch1-11/+11
Remove misleading typedef and redundant suffix from struct target.
2009-11-13reg_t -> struct regZachary T Welch1-1/+1
Remove misleading typedef and redundant suffix from struct reg.
2009-11-13armv4_5_common_t -> struct armZachary T Welch1-5/+5
Remove misleading typedef and just use struct arm.
2009-11-13etm_context_t -> struct etm_contextZachary T Welch1-1/+1
Remove misleading typedef and redundant suffix from struct etm_context.
2009-11-13reg_cache_t -> struct reg_cacheZachary T Welch1-2/+2
Remove misleading typedef and redundant suffix from struct reg_cache.
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