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| author | Antonio Borneo <borneo.antonio@gmail.com> | 2019-06-25 16:01:38 +0200 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2020-03-12 10:11:19 +0000 |
| commit | b5d2b1224fed3909aa3314339611ac5ac7ab0f82 (patch) | |
| tree | 5e38e99cfe6dbdf131b4b452948b3b889b7eac23 /src/target/armv4_5.h | |
| parent | 6900c5af4ec3f6df52227169d7d897eb14a44bca (diff) | |
| download | riscv-openocd-b5d2b1224fed3909aa3314339611ac5ac7ab0f82.zip riscv-openocd-b5d2b1224fed3909aa3314339611ac5ac7ab0f82.tar.gz riscv-openocd-b5d2b1224fed3909aa3314339611ac5ac7ab0f82.tar.bz2 | |
target/cortex_a: add hypervisor mode
Hypervisor mode is present only if the optional virtualization
extensions are available. Moreover, virtualization extensions
require that also security extensions are implemented.
Add the required infrastructure for the shadowed registers in
hypervisor mode.
Make monitor shadowed registers visible in hypervisor mode too.
Make hypervisor shadowed registers visible in hypervisor mode
only.
Check during cortex_a examine if virtualization extensions are
present and then conditionally enable the visibility of both
hypervisor and monitor modes shadowed registers.
Change-Id: I81dbb1ee8baf4c9f1a2226b77c10c8a2a7b34871
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5261
Tested-by: jenkins
Diffstat (limited to 'src/target/armv4_5.h')
| -rw-r--r-- | src/target/armv4_5.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h index 3ce4ed0..bef1cfe 100644 --- a/src/target/armv4_5.h +++ b/src/target/armv4_5.h @@ -38,7 +38,7 @@ int arm_mode_to_number(enum arm_mode mode); enum arm_mode armv4_5_number_to_mode(int number); -extern const int armv4_5_core_reg_map[8][17]; +extern const int armv4_5_core_reg_map[9][17]; #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \ (cache->reg_list[armv4_5_core_reg_map[arm_mode_to_number(mode)][num]]) |