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This logic is a little tortured, but it still passes the semihosting
tests that were the cause for the recent rewrite.
Change-Id: Ic6760bb068621ab2a49feb0cf3998fc6957b5cfc
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Fixes #485.
Change-Id: I60b3d68827ca726558bc28035c0b74c5cf0d9754
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1Gbit SPI flash on VCU118 Rev. 2.0
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* Accommodate users setting custom triggers.
RISC-V hardware supports many more triggers than gdb can communicate to
OpenOCD. Accommodate users that set triggers by writing tdata* directly,
by disable/step/reenable when a user has done that.
Note that users must set dmode in tdata1 for this behavior to work
properly. Triggers with dmode=0 are assumed to be set and handled by the
software that is being debugged.
Change-Id: Ib0751689c5553aae3a273395b10f5b98326fa066
* Enumerate triggers when resuming from a trigger
Otherwise when we connect to a target that's already halted due to a
trigger, we won't correctly step past it.
Change-Id: I23b9482fa9597af826770f9cebf247b7ba59f65c
* Also disable/reenable triggers around single step.
Gdb is smart enough to disable/step/resume if it set the triggers, but
if a user set them manually it also needs to happen.
Change-Id: I1251bd47199b6f15f61a93e3a521a53f2b677c5f
* Fix whitespace.
Change-Id: Icc240aecbc7e3e36ce4e4d784f5703304334ca13
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The name conflict is picked by compiler and it fails to compile for rv64
Fixes
src/target/riscv/riscv-011.c:1014:44: error: too many arguments provided to function-like macro invocation
static int read_csr(struct target *target, uint64_t *value, uint32_t csr)
^
Signed-off-by: Khem Raj <raj.khem@gmail.com>
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Change-Id: Ie70833a8b357c4f3ec6ae4472a77bfc409a448bf
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* Don't use MMU in M mode - https://github.com/riscv/riscv-openocd/issues/474
* Updated code based on feedback from @timsifive
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* WIP making semihosting work with -rtos hwthread.
Change-Id: Icb46f3eeedc1391e8fdc73c3ad8036f20267eb2e
* More WIP.
Change-Id: I670a6e1ba2a13a6ef2ae303a99559a16fdd1bbfb
* Fix halting due to a trigger.
Change-Id: Ie7caa8dde9518bcd5440e34cf31ed0d30ebf29ad
* Fix multicore semihosting without halt groups.
Change-Id: I53587e5234308ed2cc30a7132c86e4c94eb176c4
* WIP
Change-Id: I40630543b08d8b533726cb3f63aa60a62be8ef40
* Fix single core semihosting.
This was the last bug!
Change-Id: I593abac027fa9707f48b7f58163d7089574a0e28
* Fix whitespace.
Change-Id: I285c152970b87864c63803fae61312e5b79dfe6d
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* Speed up SBA block reads roughly 2x.
Change-Id: I4e4f5530d4abae7470fd00308361e727904367d2
* Fix whitespace.
Change-Id: I28a1269c489d051560a2455973f9a8574f35f487
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* libjaylink: discovery/usb: Add product ID (PID) 0x1061
Add the 0x1061 ID used with some HiFive1 revB boards.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* boards: sifive-hifive1-revb: Fix flash range
Fix the flash protect range to avoid errors.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* contrib: Add HiFive1 revB to udev rules
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Change-Id: I805389dc9934db5affe3c8059d9630acede956c1
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This fixes a bug where we read PC and marked it cached without actually
updating the cached value. The DPC value was correctly marked as valid
and updated.
Change-Id: Id6d3e94a96b981688b06f7f4a998019f2c02f6f5
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Change-Id: I7f7b967ccaa3d1ff05a7e7d0c2a7ba4fa7d68ac0
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* Cache accesses through riscv_[sg]et_register.
This helps a lot with the address translation code, which checks satp
over and over again. Now satp is only read once per halt. It should also
help in a few other cases (but I don't have a good test setup to really
measure the impact).
Change-Id: I90392cc60d2145a70cf6c003d6a956dc9f3c0cc4
* Fix whitespace.
Change-Id: I05c5342d8a461cd8c618a3f60296925e9e84643f
* Don't read registers that we know don't exist.
Change-Id: Ie5c6226b3d4ecb6cf8f0d8954a52fda88e6e5bdd
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If we return failure, then the caller will think something's wrong. But
it could very well be that the hardware doesn't have SATP, in which case
we should just report that the MMU is disabled.
This fixes a bug where flashing wasn't using the target algorithm
because allocating a work area failed.
Change-Id: I16e8e660036d3f8584c0b17e842c4ec8961a8410
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If a hart support both F and D, then expose the FPRs as a union of float
and double. Fixes #336.
Change-Id: I3d4503bbf9281d6380c51259388cd01d399b94d6
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Change-Id: I4373b9487ea11664d3a6ea7ea10e99ea6d337232
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The OpenOCD project looks at this, so once in a while I go through and
make sure our code is OK.
Change-Id: I50032c847f30e93604d83d6366cfad85918d6e66
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* Deal with vlenb being unreadable.
Instead of exiting during examine(), spit out a warning, and don't
expose the vector data registers. We do provide access to the vector
CSRs, because maybe they do work? It's just that we have no idea what
the size of the data registers is.
Change-Id: I6e9ffeb242e2e22fc62cb1b50782c2efb4ace0bd
* WIP
Change-Id: I46292eefe537aeaf72bdd44e4aa58298b5120b00
* Use the correct thread for memory accesses.
Previously, OpenOCD would perform RTOS memory accesses through the first
thread in the RTOS. This doesn't work if different threads have a
different memory view. For instance if `-rtos hwthread` is used, each
configured core could have address translation configured differently.
Change-Id: I61328c8f50065ecba5ce1797dbeaee482812f799
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Instead of exiting during examine(), spit out a warning, and don't
expose the vector data registers. We do provide access to the vector
CSRs, because maybe they do work? It's just that we have no idea what
the size of the data registers is.
Change-Id: I6e9ffeb242e2e22fc62cb1b50782c2efb4ace0bd
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Adds new PID (0x1051) used on board to libjaylink, and add config
and flash entry for RevB board and FE310-G002 respectively.
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Change-Id: I25029f7e83819464e71528fb4225b4761787793f
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Starting from glibc 2.30, the header file sys/sysctl.h gets
deprecated on Linux, after the commit 744e82963716 ("Linux:
Deprecate <sys/sysctl.h> and sysctl")
https://sourceware.org/git/?p=glibc.git;a=commitdiff;h=744e82963716
The associated NEWS reports
The Linux-specific <sys/sysctl.h> header and the sysctl
function have been deprecated and will be removed from a
future version of glibc.
Latest automake 1.16.1 still does not handle this case.
Current OpenOCD build fails with warning and requires configure
with "--disable-werror" to build.
Prevent including sys/sysctl.h on Linux build.
Change-Id: I5310976573352a96e5aef123352f73475f0c35fe
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5317
Tested-by: jenkins
Reviewed-by: Moritz Fischer <moritz.fischer.private@gmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Co-authored-by: Antonio Borneo <borneo.antonio@gmail.com>
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Fixes #452.
Also check that the high bits match the MSB of the virtual address.
Change-Id: Ib1d3d04db9ad9327ef71ea3736d5cf5d3b65b9c4
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This allows a user to debug code that uses software breakpoints itself.
Change-Id: If40cb626354e11703017cdf8c5919a31e83ebc3f
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* WIP
Change-Id: I0264a73b7f7d2ce89cc0b80692dbf81d9cdcc2fd
* Reading v* registers appears to work.
Can't really test it though, because gdb doesn't print them right.
Change-Id: I8d66339371c564a493d32f15c3d114b738a455c5
* Total hack to communicate registers to gdb.
Change-Id: Id06c819675f2a5bcaf751e322d95a7d71c633765
* Implement writing vector registers.
Fixed reading vector registers.
Change-Id: I8f06aa5ee5020b3213a4f68644c205c9d6b9d214
* Show gdb the actual size of the vector registers.
This length may be different per hart.
Change-Id: I92e95383da82ee7a5c995822a53d51b1ea933493
* Remove outdated todo comment.
Change-Id: Ic9158b002858f0d15a6452773b095aa5f4501128
* Removed TODO comment.
Filed #449 to track this.
Change-Id: I5277b19e545df2024f34cda39158ddf7d0d89d47
* Nicely handle some errors reading/writing V regs.
Change-Id: Ia7bb63a5f9433d9f7b46496b2c0994864cfc4a09
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Evidently this is what gdb expects.
Change-Id: I634cdbcbcfab149c1b916e3744ff4915a8f8669b
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Change-Id: I769af8323545c2c18e4253a1543e9202f0bdfabc
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* Handle DMI busy in sba write.
If we encounter DMI busy on the NOP after a read, we'll never get the
value out because DMI busy is sticky. The read must be retried, but we
don't know whether it was ever issued. Since the read has side effects
(incrementing of the address) this retry must be handled at a higher
layer. So now dmi_op_timeout can be told to retry or not, and if retry
is disabled it'll return an error when busy.
Also actually properly do the retry in dmi_op_timeout(). Previously the
code would not reissue the command and end up returning a garbage value.
Change-Id: I3b52ebd51ebbbedd6e425676ac861b57fbe711b1
* Fix whitespace.
Change-Id: Icb76d964e681b22346368d224d1930c9342343f3
* Handle a few more DMI busy cases.
Change-Id: I8503a44e4bf935c0ebfff0d598fe4c322fda702a
* Explain when to use dmi_op_timeout(retry).
Change-Id: I1a5c6d76ac41a84472a8f79faecb2f48105191ff
* dmi_reset does not affect the current transaction.
That means the retry scheme we had been using works fine. This does
contain some minor tweaks, and now we pass my tests which hammer the DMI
busy case harder.
Change-Id: I13eee384dbba82bc5a5b1d387c75c547afe557b5
* Remove unnecessary changes to make the PR readable
Change-Id: I87079876e6965563cf590e3936b3595aeab8715d
* Move idle to end of line...
... because we go through run-test/idle after the scan.
Change-Id: I21a8cff22471f0b895d8cd8d25373dced9bf1ca9
* Remove unused code.
Change-Id: I07a7cdd2d64ca40a4fe181111a34cf55ff1928d1
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The original OpenOCD code issued FENCE & FENCE.i twice for the current
hart (which is harmless, but takes time).
Avoiding this extra FENCE is a slight performance improvement. Per my rough
measurements, this improves performance of certain debugger actions
(single-stepping) by approx. 20% in single-hart systems.
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Change-Id: I00f0d2a3c79a431e1aa49c7478fa6c17e2fa5256
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* riscv: Fix bugs. Do not touch SATP if there is no MMU.
In some platform, there is no SATP register at all.
OpenOCD will report unexpected errors if SATP is unreadable.
So, use 'riscv_enable_virtual' to guard SATP access.
* riscv: fix format typo.
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* riscv: translate virtual address to physical address.
* riscv: fix formatting errors.
* riscv: fix build errors.
* riscv: Remove redundant command for virtual address access.
* Revert "riscv: Remove redundant command for virtual address access."
This reverts commit 990d09eac37d2effcfc5c0d0b5c99678f45e7d7f.
* riscv: Change command disable_virt2phys to set_enable_virt2phys
1. Avoid double negative logic to make users easy to use.
2. Add document about new comomand 'riscv set_enable_virt2phys on|off'
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OpenOCD can't deal with systems that have more than 32 harts.
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Saves 1.4MiB of RAM too, with just 1 hart configured.
Change-Id: I68d8c003a67c280b62ff6c9285ac6f54865f99f2
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Change-Id: I7fc5dc0ebe91497ffdefe480a409dc0feacfb49f
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Abstract write size (aarsize) to shall always match the real
size of the register. This is because abstract write of smaller size
than the register need not be supported per spec (pg. 13 of RISC-V
External Debug Support ver. 0.13.2).
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Fix memory access on 64-bit targets with no progbuf and sba that
supports 32-bit accesses but not 64-bit accesses. Bug was introduced in #419.
This fixes https://github.com/riscv/riscv-tests/issues/217.
Change-Id: Ib5ddf9886b77e3d58fe1d891b560ad03d5a46da1
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When allocating scratch memory within RISC-V target
(scratch_reserve()), take into account whether progbuf
is writable or not, as determined by examine_progbuf().
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* 64-bit progbuf memory reads work.
Change-Id: Ia3dbc0ee39a31ed0e5c38bbb3d9e089b2533f399
* 64-bit writes work.
Change-Id: Iae78711d715b6682817bb7cce366b0094bda8b23
* Let targets indicate number of supported data bits.
This is used by the default memory read/write functions when creating an
aligned block.
I'm adding this mainly to ensure I get coverage of the 64-bit progbuf
memory read/write code.
Change-Id: Ie5909fe537c9ec3360a8d2837f84be00a63de77b
* Make mingw32 happy.
Change-Id: Iade8c1fdfc72ccafc82f2f34923577032b668916
* WIP >16MB flashing.
Change-Id: Ibef9244f8573d2fbf19b80e5db7c2d3a10da59b5
* >16MB flashing works on Hi5 Unleashed
But now flashing HiFive1 is broken.
Change-Id: If939c9e21cf793ae727f3335205abd261a998c0c
* Fix off-by-one error on bank size.
Change-Id: I0e6e49db8c1bfddb2c5f67d40f62111246db8dcb
* Fix formatting.
Change-Id: I4211f9328c7d11ea659be9588a81aa2cd59017f9
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* fix for batch scans not honoring presence of BSCAN tunnel
* fix formatting to placate checkpatch
* replace DIM with ARRAY_SIZE
* Refactor code that adds a bscan tunneled scan.
* Move bscan tunnel context to the batch structure, and in array
form, one per scan
* adjust code that was inconsistent with project code formatting standards
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* 64-bit progbuf memory reads work.
Change-Id: Ia3dbc0ee39a31ed0e5c38bbb3d9e089b2533f399
* 64-bit writes work.
Change-Id: Iae78711d715b6682817bb7cce366b0094bda8b23
* Let targets indicate number of supported data bits.
This is used by the default memory read/write functions when creating an
aligned block.
I'm adding this mainly to ensure I get coverage of the 64-bit progbuf
memory read/write code.
Change-Id: Ie5909fe537c9ec3360a8d2837f84be00a63de77b
* Make mingw32 happy.
Change-Id: Iade8c1fdfc72ccafc82f2f34923577032b668916
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Change-Id: I38f10d34b163eb7d0bf44b5717bbb027b0e43e76
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Combine SMP group registers into one list for gdb
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This makes behavior when you've configured an SMP group of heterogeneous
targets a bit less weird. (You still shouldn't be doing that, since gdb
and who knows what else assumes that the targets in an SMP group are
homogeneous.)
Specifically, if you have a HiFive Unleashed board (where the first core
is fairly basic and the other 4 or more full-featured) this lets you
connect to all 5, and still have access to the FPU etc. on the higher
numbered cores.
Change-Id: I2e01f63f8753f78c29d7f414ea603e02bf0390e0
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The compliance test is poorly supported.
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In reaction to #412.
Change-Id: I183bd8b4995c04e44cbc4f1c475eae391030fae6
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Get latest code from upstream
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We don't want to enforce code style on libjaylink, which in mainline is
a subrepository.
Change-Id: Ic72dff4b56f5781dd1ba94519eb4b067903ceaae
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Change-Id: I3a314488136ec47611d660140fb5dd70c00be59c
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