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| author | Tim Newsome <tim@sifive.com> | 2020-05-06 08:43:59 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-05-06 08:43:59 -0700 |
| commit | 0c3e50a06a78a721ce56b13ca90c3e8699a17492 (patch) | |
| tree | 7db75e6c70a9090a9a201398274be9974bc52cd9 | |
| parent | 55dd7e83cad26716b04037309bbde3476de43f4d (diff) | |
| download | riscv-openocd-0c3e50a06a78a721ce56b13ca90c3e8699a17492.zip riscv-openocd-0c3e50a06a78a721ce56b13ca90c3e8699a17492.tar.gz riscv-openocd-0c3e50a06a78a721ce56b13ca90c3e8699a17492.tar.bz2 | |
Don't cache PC, but do cache DPC. (#473)
This fixes a bug where we read PC and marked it cached without actually
updating the cached value. The DPC value was correctly marked as valid
and updated.
Change-Id: Id6d3e94a96b981688b06f7f4a998019f2c02f6f5
| -rw-r--r-- | src/target/riscv/riscv.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 68ff2a4..c939a9c 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -3015,13 +3015,15 @@ static bool gdb_regno_cacheable(enum gdb_regno regno, bool write) /* GPRs, FPRs, vector registers are just normal data stores. */ if (regno <= GDB_REGNO_XPR31 || (regno >= GDB_REGNO_FPR0 && regno <= GDB_REGNO_FPR31) || - (regno >= GDB_REGNO_V0 && regno <= GDB_REGNO_V31) || - regno == GDB_REGNO_PC) + (regno >= GDB_REGNO_V0 && regno <= GDB_REGNO_V31)) return true; /* Most CSRs won't change value on us, but we can't assume it about rbitrary * CSRs. */ switch (regno) { + case GDB_REGNO_DPC: + return true; + case GDB_REGNO_VSTART: case GDB_REGNO_VXSAT: case GDB_REGNO_VXRM: @@ -3029,7 +3031,6 @@ static bool gdb_regno_cacheable(enum gdb_regno regno, bool write) case GDB_REGNO_VL: case GDB_REGNO_VTYPE: case GDB_REGNO_MISA: - case GDB_REGNO_DPC: case GDB_REGNO_DCSR: case GDB_REGNO_DSCRATCH: case GDB_REGNO_MSTATUS: |