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9 daysMerge pull request #1096 from en-sc/en-sc/run-batch-busyEvgeniy Naydanov1-3/+7
target/riscv: reset `dmi.busy` after batches
9 daysMerge pull request #1083 from en-sc/en-sc/deprecate-reset-timeoutEvgeniy Naydanov5-77/+41
target/riscv: deprecate `riscv set_reset_timeout_sec`
9 daysMerge pull request #1081 from en-sc/en-sc/sb_read_v1Evgeniy Naydanov1-62/+32
target/riscv: use batch interface in `read_memory_bus_v1()`
9 daysMerge pull request #1093 from en-sc/en-sc/v-ext-csrsEvgeniy Naydanov1-0/+8
target/riscv: vector CSRs are optional
14 daystarget/riscv: deprecate `riscv set_reset_timeout_sec`Evgeniy Naydanov5-77/+41
Change-Id: I46bf3e4dab2a99c97b7ab133a85c13332365f9b7 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
14 daysMerge pull request #1082 from en-sc/en-sc/sbcs-readEvgeniy Naydanov1-20/+8
target/riscv: simplify `sbcs` read in `write_memory_bus_v1()`
2024-07-03target/riscv: reset `dmi.busy` after batchesEvgeniy Naydanov1-3/+7
Additionally, avoid calling `riscv_batch_finished_scans()` / decrementing reset counter if the batch run failed. Change-Id: I3eb7b23e4dc029090e92e3e543719824add623e1 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-07-03target/riscv: vector CSRs are optionalEvgeniy Naydanov1-0/+8
This is a fix to a mistake made in ea7e17491d56ced52ab803949b23aa9579bb3c57. The newly introduced `gdb_regno_exist()` function was missing a part regarding vector CSRs. Link: https://github.com/riscv-collab/riscv-openocd/pull/1022/commits/ea7e17491d56ced52ab803949b23aa9579bb3c57#diff-b4aa16f9e42cb8f0934baa7c8e0ec9c70a369bef98b99b26ae2e896c8aa95d6aL6163-L6171 Change-Id: I0361ea4dce8df5be748e2c6e7e6838029d3a7120 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-07-03target/riscv: use batch interface in `read_memory_bus_v1()`Evgeniy Naydanov1-62/+32
Fixes #1080 Change-Id: Ifc1a48fcd0b28f7cdb1e5ad3cbd20d53ea3560a5 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-07-03Merge pull request #1087 from en-sc/en-sc/delay-typesEvgeniy Naydanov3-110/+167
target/riscv: replace `info->*_delay` with `riscv_scan_delays`
2024-07-03Merge pull request #1084 from en-sc/en-sc/ref-reg-filesEvgeniy Naydanov17-1486/+1678
target/riscv: separate register cache stuff into files
2024-07-02target/riscv: simplify `sbcs` read in `write_memory_bus_v1()`Evgeniy Naydanov1-20/+8
Change-Id: Ifc94614eaaa191925d44d8963cd6d1e5e8427cba Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-07-02target/riscv: separate register cache stuff into filesEvgeniy Naydanov17-1486/+1678
This commit creates file structure for register cache related functions. Specifically: * `riscv_reg.h` -- general interface to registers. Safe to use after register cache initialization is successful. * `riscv_reg_impl.h` -- helper functions to use while implementing register cache initialization. * `riscv_reg.c` -- definitions of functions from `riscv_reg.h` and `riscv_reg_impl.h`. * `riscv-011_reg.h` -- register cache interface specific to 0.11 targets. * `riscv-013_reg.h` -- register cache interface specific to 0.13+ targets. * `riscv-011/0.13.h` -- version-specific methods used to access registers. Will be extended as needed once other functionality (not related to register access) is separated (e.g. DM/DTM specific stuff). Change-Id: I7918f78d0d79b97188c5703efd0296660e529f2a Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-07-01target/riscv: replace `info->*_delay` with `riscv_scan_delays`Evgeniy Naydanov3-110/+167
* Improves error handling. * Handles possible overflow. Change-Id: Iae0df9356af06cc21dc71c86ba7c923d1515bdc5 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-07-01Merge pull request #1085 from en-sc/en-sc/checkpatch-check-gitEvgeniy Naydanov1-7/+1
.github/workflows: check git revisions instead of a diff
2024-07-01Merge pull request #1094 from en-sc/en-sc/from_upstreamEvgeniy Naydanov62-843/+1469
Merge up to ad87fbd1cf28760795c4e18f3318a2d720e5a8a6 from upstream
2024-06-25Merge up to ad87fbd1cf28760795c4e18f3318a2d720e5a8a6 from upstreamEvgeniy Naydanov62-843/+1469
Conflicts: * `doc/openocd.texi`: due to d382c95d57c0ad9ed2dcc83c95404babb7647708, resolved by selecting the upstream version. * `src/server/gdb_server.c`: between 944fe66f104e356c5fcd2b5c25200cebef9b389c and 92e8823ebdb6d01b41bb5d79af49501d525acd1d. Resolved by adopting the use of `LOG_TARGET_*`. * `src/target/target.c`: between 639e68a621b7ae8c4a296ca7e45b47075268fded and c5358c84ad0d3e7497498e0457cec7785f72910a, selected the version from `riscv-openocd`. Change-Id: Ic1327f25e147945e0ec82947a82452501e8ee5de
2024-06-25tcl/interface: support for Raspberry Pi 5Tomas Vanek3-12/+51
Make sure raspberrypi-native.cfg cannot be used on RPi5. Add raspberrypi5-gpiod.cfg which uses linuxgpiod adapter driver. Issue a warning if PCIe is in power save mode. While on it, re-format warnings issued from Tcl to look similar to LOG_WARNING() output. Change-Id: If19b0350bd5fff83d9a0c65999e33b161fb6957a Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/8333 Tested-by: jenkins Reviewed-by: Jonathan Bell <jonathan@raspberrypi.com>
2024-06-23Remove other '_s' suffix from structsAntonio Borneo6-16/+16
Most of the work is already done by [1]. Remove few more '_s' suffix and also fix some comment referring to the old name of the struct. Link: https://review.openocd.org/c/openocd/+/8340 Change-Id: Ifddc401c3b05e62ece3aa7926af1e78f0c4a671e Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8341 Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2024-06-23Remove '_s' suffix from structsMarc Schink9-186/+186
Change-Id: I956acce316e60252b317daa41274403d87f704b8 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8340 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-06-23server/gdb: Use LOG_TARGET_xxx() to show target nameMarc Schink1-20/+18
The output "gdb port disabled" is confusing without reference to the target. Use LOG_TARGET_INFO() to output the target name. While at it, use LOG_TARGET_xxx() for all log statements where the target name is already used. Change-Id: I70b134145837db623e008a4a6c0be0008d9a0d87 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8313 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2024-06-23remote_bitbang: fix assertion failure for the cases when connection is ↵Timur Golubovich1-1/+8
abruptly terminated Changes affect the function remote_bitbang_fill_buf. When read_socket returns 0, socket reached EOF and there is no data to read. But if request was blocking, the caller expected some data. Such situations should be treated as ERROR. Change-Id: I02ed484e61fb776c1625f6e36ab14c85891939b2 Signed-off-by: Timur Golubovich <timur.golubovich@syntacore.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8325 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-06-23itm: fix default initializationAntonio Borneo3-12/+16
Commit f9509c92dba3 ("itm: rework itm commands before 'init'") ignores the default enable of ITM channel 0, that is applied when no 'itm port[s]' is issued. Call armv7m_trace_itm_config() unconditionally to handle it. Change-Id: I3e85d0b063ed38c1552f6af9ea9eea2e76aa9025 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reported-by: Paul Fertser <fercerpav@gmail.com> Fixes: f9509c92dba3 ("itm: rework itm commands before 'init'") Reviewed-on: https://review.openocd.org/c/openocd/+/7900 Reviewed-by: <post@frankplowman.com> Tested-by: jenkins
2024-06-23target: aarch64: access reg SPSR_EL1 only in EL1, EL2 and EL3Antonio Borneo1-7/+15
The register SPSR_EL1 is accessible and it's content is relevant only when the target is in EL1 or EL2 or EL3. Plus, the register is 64 bits wide. Without this patch, an error: Error: Opcode 0xd5384000, DSCR.ERR=1, DSCR.EL=1 is triggered by GDB register window or through GDB command x/p $SPSR_EL1 or through OpenOCD command reg SPSR_EL1 Detect the EL and return error if the register cannot be accessed. Handle the register as 64 bits. Change-Id: Ia0f984d52920cc32b8ee31157d62c13dea616a3a Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8276 Tested-by: jenkins
2024-06-23target: aarch64: access reg ESR_EL1 only in EL1, EL2 and EL3Antonio Borneo1-7/+15
The register ESR_EL1 is accessible and it's content is relevant only when the target is in EL1 or EL2 or EL3. Plus, the register is 64 bits wide. Without this patch, an error: Error: Opcode 0xd5385200, DSCR.ERR=1, DSCR.EL=1 is triggered by GDB register window or through GDB command x/p $ESR_EL1 or through OpenOCD command reg ESR_EL1 Detect the EL and return error if the register cannot be accessed. Handle the register as 64 bits. Change-Id: Icd65470c279e5cfd03091db6435cdaa1c447644c Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8275 Tested-by: jenkins
2024-06-23target: aarch64: access reg ELR_EL1 only in EL1, EL2 and EL3Antonio Borneo1-0/+10
The register ELR_EL1 is accessible and it's content is relevant only when the target is in EL1 or EL2 or EL3. Without this patch, an error: Error: Opcode 0xd5384020, DSCR.ERR=1, DSCR.EL=1 is triggered by GDB register window or through GDB command x/p $ELR_EL1 or through OpenOCD command reg ELR_EL1 Detect the EL and return error if the register cannot be accessed. Change-Id: I402dda4cd9dae502b05572fc6c1a8f0edf349bb1 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8274 Tested-by: jenkins
2024-06-23target: aarch64: access reg SPSR_EL2 only in EL2 and EL3Antonio Borneo1-7/+15
The register SPSR_EL2 is accessible and it's content is relevant only when the target is in EL2 or EL3. Virtualization SW in EL1 can also access it, but this either triggers a trap to EL2 or returns SPSR_EL1. Debugger should not mix the real SPSR_EL2 with the virtual register. Plus, the register is 64 bits wide. Without this patch, an error: Error: Opcode 0xd53c4000, DSCR.ERR=1, DSCR.EL=1 is triggered by GDB register window or through GDB command x/p $SPSR_EL2 or through OpenOCD command reg SPSR_EL2 Detect the EL and return error if the register cannot be accessed. Handle the register as 64 bits. Change-Id: If3792296b36282c08d597dd46cfe044d6b8288ea Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8273 Tested-by: jenkins
2024-06-23target: aarch64: access reg ESR_EL2 only in EL2 and EL3Antonio Borneo1-7/+15
The register ESR_EL2 is accessible and it's content is relevant only when the target is in EL2 or EL3. Virtualization SW in EL1 can also access it, but this either triggers a trap to EL2 or returns ESR_EL1. Debugger should not mix the real ESR_EL2 with the virtual register. Plus, the register is 64 bits wide. Without this patch, an error: Error: Opcode 0xd53c5200, DSCR.ERR=1, DSCR.EL=1 is triggered by GDB register window or through GDB command x/p $ESR_EL2 or through OpenOCD command reg ESR_EL2 Detect the EL and return error if the register cannot be accessed. Handle the register as 64 bits. Change-Id: Icb32b44886d50907f29b068ce61e4be8bed10208 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8272 Tested-by: jenkins
2024-06-23target: aarch64: access reg ELR_EL2 only in EL2 and EL3Antonio Borneo1-0/+10
The register ELR_EL2 is accessible and it's content is relevant only when the target is in EL2 or EL3. Virtualization SW in EL1 can also access it, but this either triggers a trap to EL2 or returns ELR_EL1. Debugger should not mix the real ELR_EL2 with the virtual register. Without this patch, an error: Error: Opcode 0xd53c4020, DSCR.ERR=1, DSCR.EL=1 is triggered by GDB register window or through GDB command x/p $ELR_EL2 or through OpenOCD command reg ELR_EL2 Detect the EL and return error if the register cannot be accessed. Change-Id: Idf02b42a7339df83260c1e44ceabbb05fbf392b9 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8271 Tested-by: jenkins
2024-06-23target: aarch64: access reg SPSR_EL3 only in EL3Antonio Borneo1-7/+15
The register SPSR_EL3 is accessible and it's content is relevant only when the target is in EL3. Plus, the register is 64 bits wide. Without this patch, an error: Error: Opcode 0xd53e4000, DSCR.ERR=1, DSCR.EL=1 is triggered by GDB register window or through GDB command x/p $SPSR_EL3 or through OpenOCD command reg SPSR_EL3 Detect the EL and return error if the register cannot be accessed. Handle the register as 64 bits. Change-Id: I00849d99feeb96589c426fcafda98127dbd19a67 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8270 Tested-by: jenkins
2024-06-23target: aarch64: access reg ESR_EL3 only in EL3Antonio Borneo1-9/+17
The register ESR_EL3 is accessible and it's content is relevant only when the target is in EL3. Plus, the register is 64 bits wide. Without this patch, an error: Error: Opcode 0xd53e5200, DSCR.ERR=1, DSCR.EL=1 is triggered by GDB register window or through GDB command x/p $ESR_EL3 or through OpenOCD command reg ESR_EL3 Detect the EL and return error if the register cannot be accessed. Handle the register as 64 bits. Drop the FIXME comment on Aarch32 case, as the register exists in Aarch64 only. Change-Id: Ie8c69dc7b50ae81a52506cf151c8e64e15752d0d Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8269 Tested-by: jenkins
2024-06-23target: aarch64: access reg ELR_EL3 only in EL3Antonio Borneo1-0/+12
The register ELR_EL3 is accessible and it's content is relevant only when the target is in EL3. Without this patch, an error: Error: Opcode 0xd53e4020, DSCR.ERR=1, DSCR.EL=1 is triggered by GDB register window or through GDB command x/p $ELR_EL3 or through OpenOCD command reg ELR_EL3 Detect the EL and return error if the register cannot be accessed. Change-Id: I545abb196e5c34e462c7e5d5d3ec952e588642da Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8268 Tested-by: jenkins
2024-06-23target: armv8_dpm: silence error on register R/WAntonio Borneo1-2/+2
The command 'gdb_report_register_access_error' is used to silence errors while reading registers and not reporting them to GDB. Nevertheless, the error is printed by a LOG_ERROR() in armv8_dpm. Change the message to LOG_DEBUG(). It will still cause the error to be propagated and eventually printed by the caller (e.g. by the command 'reg'). Change-Id: Ic0db74fa28235d686ddd21a5960c52ae003e0931 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8267 Tested-by: jenkins
2024-06-23target: aarch64: align armv8_read_reg() and armv8_read_reg32()Antonio Borneo1-4/+8
These functions are today always called with non-NULL parameter regval, so the actual check is not needed. Anyway, for any future code change, check the parameter at the entry of the functions and return error if it is not valid. Simplify the check to assign the result value and align the code of the two functions. Change-Id: Ie4d98063006d70d9e2bcfc00bc930133caf33515 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8266 Tested-by: jenkins
2024-06-17Merge pull request #1089 from en-sc/en-sc/batch-select-dmiAnatoly Parshintsev1-0/+2
target/riscv: select DMI IR on batch access
2024-06-17target: Do not use LOG_USER() for error messagesMarc Schink1-4/+3
Use LOG_TARGET_ERROR() to print the error messages and additionally add a reference to the related target. Change-Id: I06722f3911ef4034fdd05dc9b0e2571b01b657a4 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8314 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
2024-06-17target/cortex_m: allow poll quickly get out of TARGET_RESET stateTomas Vanek1-1/+5
cortex_m_poll_one() detects reset testing S_RESET_ST sticky bit. If the signal comes unexpectedly, poll must return TARGET_RESET state. On the contrary in case of polling inside of an OpenOCD reset command, TARGET_RESET has been has already been set and we need to get out of it as quickly as possible. The original code needs 2 polls: the first clears S_RESET_ST and keeps TARGET_RESET state, the current TARGET_RUNNING or TARGET_HALTED is reflected as late as the second poll is done. Change the logic to keep in TARGET_RESET only when necessary. See also [1] Link: [1] 8284: tcl/target: ti_cc3220sf: Use halt for CC3320SF targets | https://review.openocd.org/c/openocd/+/8284 Fixes: https://sourceforge.net/p/openocd/tickets/360/ Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Change-Id: I759461e5f89ca48a6e16e4b4101570260421dba1 Reviewed-on: https://review.openocd.org/c/openocd/+/8285 Tested-by: jenkins Reviewed-by: Dhruva Gole <d-gole@ti.com>
2024-06-15pld: small documentation fixes.Daniel Anselmi1-3/+3
Change-Id: I969f51c38fc0c34c6bdba98b0e618d7f28ea4052 Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/8084 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2024-06-15pld/intel: remove idcodes from intel.cDaniel Anselmi9-265/+153
Remove list of id codes for all families. Maintain a list with id, bscan-length and check position in the tcl config files for each family. The Intel FPGA Driver option 'family' is not otional anymore. Change-Id: I9a40a041069e84f6b4728f2cd715756a36759c89 Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/8083 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2024-06-15pld/intel: remove duplicated codeDaniel Anselmi1-3/+0
Change-Id: I043d16c77ce97d3e888774747ed6bfc4c7e63c04 Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/8082 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-06-15tcl/board: Support for Digilent Nexys 2 boardGeorge Voicu1-0/+30
Support Digilent Nexys 2 board JTAG chain Signed-off-by: George Voicu <razvanvg@hotmail.com> Change-Id: I350f80b49303c4b0402d93ebc120a591ef727551 Reviewed-on: https://review.openocd.org/c/openocd/+/7336 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-06-15tcl/fpga: Support for Xilinx Spartan3 series devicesGeorge Voicu1-0/+43
Tap definition for Xilinx Spartan 3/3E/3A/3AN/3A-DSP devices. Signed-off-by: George Voicu <razvanvg@hotmail.com> Change-Id: Ieda2b61fc270840f9192976697fcac259c45e3b8 Reviewed-on: https://review.openocd.org/c/openocd/+/7335 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2024-06-15tcl/fpga/xilinx-dna: Support for reading Spartan3 DNA codeGeorge Voicu1-0/+6
Add Xilinx Spartan3 ISC_DNA instruction Signed-off-by: George Voicu <razvanvg@hotmail.com> Change-Id: Iaddb079c9fdd1b91c65def36878fe81783098696 Reviewed-on: https://review.openocd.org/c/openocd/+/7331 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-06-15target/arm_tpiu_swo: Fix memory leak on errorAntonio Borneo1-4/+2
In case of fail to allocate 'obj->name', the memory allocated for 'obj->out_filename' is not freed, thus leaking. Since 'obj' is allocated with calloc(), thus zeroed, switch to use the common error exit path for both allocations of 'obj->name' and 'obj->out_filename'. Fixes: 2506ccb50915 ("target/arm_tpiu_swo: Fix division by zero") Change-Id: I412f66ddd7bf7d260cee495324058482b26ff0c5 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8300 Tested-by: jenkins Reviewed-by: zapb <dev@zapb.de>
2024-06-15fix GCC's `-Wcalloc-transposed-args` warningEvgeniy Naydanov10-13/+13
GCC 14.1.0 warns about calls to `calloc()` with element size as the first argument. Link: https://gcc.gnu.org/onlinedocs/gcc-14.1.0/gcc/Warning-Options.html#index-Wcalloc-transposed-args Change-Id: I7d44a74a003ee6ec49d165f91727972478214587 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8301 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2024-06-14target/riscv: select DMI IR on batch access.Evgeniy Naydanov1-0/+2
Without the selection the TAP can be left in bypass. Change-Id: I79c6bf74802dc9c9475947d1787a3d0b797f3952 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-06-10Merge pull request #1073 from en-sc/en-sc/abs-reg-batchEvgeniy Naydanov3-100/+308
target/riscv: write registers using batch
2024-06-08flash/nor/nrf5: handle ERROR_WAIT during nRF91 flash eraseTomas Vanek1-0/+22
Erase is initiated by write to a flash address. Due to the silicon errata of nRF91 the write stalls the bus until the page erase is finished (takes up to 87ms). If the adapter does not handle SWD WAIT properly, the following read in nrf5_wait_for_nvmc() returns ERROR_WAIT. Wait for fixed time before accessing AP. Not nice, but the only working solution until all adapters handle SWD WAIT. If the fixed wait does not suffice, continue the wait loop after a delay. It makes some unnecessary noise however erase works. Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Change-Id: I63faf38dad79440a0117ed79930442bd2843c6db Reviewed-on: https://review.openocd.org/c/openocd/+/8115 Reviewed-by: Tomáš Beneš <tomas@dronetag.cz> Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-06-08flash/nor/nrf5: show proper SoC type on newer nRF91 devicesTomas Vanek1-4/+38
Since nRF9160 Product Specification v2.1 the new UICR SIPINFO fields should be preferred over UICR INFO. Tested on nRF9161. Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Change-Id: Ib8005b3b6292aa20fa83c1dcebd2de27df58b661 Reviewed-on: https://review.openocd.org/c/openocd/+/8114 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-06-08tcl/target: add nRF53 and nRF91 config filesTomas Vanek3-0/+295
Both devices can be configured with or without SWD multidrop. nRF53 network core is examined on demand to avoid problems when the core is forced off. Change-Id: I08f88ff48ff7ac592e9214b89ca8e5e9428573a5 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/8113 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
generated by cgit v1.1 at 2024-07-18 05:25:03 +0000