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| author | Antonio Borneo <borneo.antonio@gmail.com> | 2024-05-14 14:17:39 +0200 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2024-06-23 09:29:29 +0000 |
| commit | f39f136e012589212b463af4ef1ac7d855901810 (patch) | |
| tree | 92d37551e8efdcec5101087d949968b5e56b438b | |
| parent | 2a63fabd095044f0a05cf69a34300409809f676b (diff) | |
| download | riscv-openocd-f39f136e012589212b463af4ef1ac7d855901810.zip riscv-openocd-f39f136e012589212b463af4ef1ac7d855901810.tar.gz riscv-openocd-f39f136e012589212b463af4ef1ac7d855901810.tar.bz2 | |
target: aarch64: access reg ELR_EL1 only in EL1, EL2 and EL3
The register ELR_EL1 is accessible and it's content is relevant
only when the target is in EL1 or EL2 or EL3.
Without this patch, an error:
Error: Opcode 0xd5384020, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $ELR_EL1
or through OpenOCD command
reg ELR_EL1
Detect the EL and return error if the register cannot be accessed.
Change-Id: I402dda4cd9dae502b05572fc6c1a8f0edf349bb1
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8274
Tested-by: jenkins
| -rw-r--r-- | src/target/armv8.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/target/armv8.c b/src/target/armv8.c index b622dc9..1767470 100644 --- a/src/target/armv8.c +++ b/src/target/armv8.c @@ -315,6 +315,11 @@ static int armv8_read_reg(struct armv8_common *armv8, int regnum, uint64_t *regv value_64 = value; break; case ARMV8_ELR_EL1: + if (curel < SYSTEM_CUREL_EL1) { + LOG_DEBUG("ELR_EL1 not accessible in EL%u", curel); + retval = ERROR_FAIL; + break; + } retval = dpm->instr_read_data_r0_64(dpm, ARMV8_MRS(SYSTEM_ELR_EL1, 0), &value_64); break; @@ -463,6 +468,11 @@ static int armv8_write_reg(struct armv8_common *armv8, int regnum, uint64_t valu break; /* registers clobbered by taking exception in debug state */ case ARMV8_ELR_EL1: + if (curel < SYSTEM_CUREL_EL1) { + LOG_DEBUG("ELR_EL1 not accessible in EL%u", curel); + retval = ERROR_FAIL; + break; + } retval = dpm->instr_write_data_r0_64(dpm, ARMV8_MSR_GP(SYSTEM_ELR_EL1, 0), value_64); break; |