pld/intel: remove idcodes from intel.c

Remove list of id codes for all families.
Maintain a list with id, bscan-length and check position
in the tcl config files for each family.

The Intel FPGA Driver option 'family' is not otional anymore.

Change-Id: I9a40a041069e84f6b4728f2cd715756a36759c89
Signed-off-by: Daniel Anselmi <danselmi@gmx.ch>
Reviewed-on: https://review.openocd.org/c/openocd/+/8083
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins

9 files changed, 153 insertions, 265 deletions

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 8c9f3ff..03fa944 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -8886,13 +8886,12 @@ For the option @option{-family} @var{name} is one of @var{trion|titanium}.
 @end deffn
 
 
-@deffn {FPGA Driver} {intel} [@option{-family} <name>]
+@deffn {FPGA Driver} {intel} @option{-family} <name>
 This driver can be used to load the bitstream into Intel (former Altera) FPGAs.
 The families Cyclone III, Cyclone IV, Cyclone V, Cyclone 10, Arria II are supported.
 @c Arria V and Arria 10, MAX II, MAX V, MAX10)
 
-For the option @option{-family} @var{name} is one of @var{cycloneiii cycloneiv cyclonev cyclone10 arriaii}.
-This is needed when the JTAG ID of the device is ambiguous (same ID is used for chips in different families).
+The option @option{-family} @var{name} is one of @var{cycloneiii cycloneiv cyclonev cyclone10 arriaii}.
 
 As input file format the driver supports a '.rbf' (raw bitstream file) file. The '.rbf' file can be generated
 from a '.sof' file with @verb{|quartus_cpf -c blinker.sof blinker.rbf|}
diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c
index 7995529..1a4c4b7 100644
--- a/src/jtag/tcl.c
+++ b/src/jtag/tcl.c
@@ -760,8 +760,9 @@ static const struct command_registration jtag_subcommand_handlers[] = {
 		.mode = COMMAND_EXEC,
 		.handler = handle_jtag_configure,
 		.help = "Return any Tcl handler for the specified "
-			"TAP event.",
-		.usage = "tap_name '-event' event_name",
+			"TAP event or the value of the IDCODE found in hardware.",
+		.usage = "tap_name '-event' event_name | "
+		    "tap_name '-idcode'",
 	},
 	{
 		.name = "names",
diff --git a/src/pld/intel.c b/src/pld/intel.c
index fe85cd6..a4bdabe 100644
--- a/src/pld/intel.c
+++ b/src/pld/intel.c
@@ -37,142 +37,11 @@ struct intel_pld_device {
 	enum intel_family_e family;
 };
 
-struct intel_device_parameters_elem {
-	uint32_t id;
-	unsigned int boundary_scan_length;
-	int checkpos;
-	enum intel_family_e family;
-};
-
-static const struct intel_device_parameters_elem intel_device_parameters[] = {
-	{0x020f10dd,  603,  226, INTEL_CYCLONEIII}, /* EP3C5 EP3C10 */
-	{0x020f20dd, 1080,  409, INTEL_CYCLONEIII}, /* EP3C16 */
-	{0x020f30dd,  732,  286, INTEL_CYCLONEIII}, /* EP3C25 */
-	{0x020f40dd, 1632,  604, INTEL_CYCLONEIII}, /* EP3C40 */
-	{0x020f50dd, 1164,  442, INTEL_CYCLONEIII}, /* EP3C55 */
-	{0x020f60dd, 1314,  502, INTEL_CYCLONEIII}, /* EP3C80 */
-	{0x020f70dd, 1620,  613, INTEL_CYCLONEIII}, /* EP3C120*/
-	{0x027010dd, 1314,  226, INTEL_CYCLONEIII}, /* EP3CLS70 */
-	{0x027000dd, 1314,  226, INTEL_CYCLONEIII}, /* EP3CLS100 */
-	{0x027030dd, 1314,  409, INTEL_CYCLONEIII}, /* EP3CLS150 */
-	{0x027020dd, 1314,  409, INTEL_CYCLONEIII}, /* EP3CLS200 */
-
-	{0x020f10dd,  603,  226, INTEL_CYCLONEIV}, /* EP4CE6 EP4CE10 */
-	{0x020f20dd, 1080,  409, INTEL_CYCLONEIV}, /* EP4CE15 */
-	{0x020f30dd,  732,  286, INTEL_CYCLONEIV}, /* EP4CE22 */
-	{0x020f40dd, 1632,  604, INTEL_CYCLONEIV}, /* EP4CE30 EP4CE40 */
-	{0x020f50dd, 1164,  442, INTEL_CYCLONEIV}, /* EP4CE55 */
-	{0x020f60dd, 1314,  502, INTEL_CYCLONEIV}, /* EP4CE75 */
-	{0x020f70dd, 1620,  613, INTEL_CYCLONEIV}, /* EP4CE115 */
-	{0x028010dd,  260,  229, INTEL_CYCLONEIV}, /* EP4CGX15 */
-	{0x028120dd,  494,  463, INTEL_CYCLONEIV}, /* EP4CGX22 */
-	{0x028020dd,  494,  463, INTEL_CYCLONEIV}, /* EP4CGX30 */
-	{0x028230dd, 1006,  943, INTEL_CYCLONEIV}, /* EP4CGX30 */
-	{0x028130dd, 1006,  943, INTEL_CYCLONEIV}, /* EP4CGX50 */
-	{0x028030dd, 1006,  943, INTEL_CYCLONEIV}, /* EP4CGX75 */
-	{0x028140dd, 1495, 1438, INTEL_CYCLONEIV}, /* EP4CGX110 */
-	{0x028040dd, 1495, 1438, INTEL_CYCLONEIV}, /* EP4CGX150 */
-
-	{0x02b150dd,  864, 163, INTEL_CYCLONEV}, /* 5CEBA2F23 5CEBA2F17 5CEFA2M13 5CEFA2F23 5CEBA2U15 5CEFA2U19 5CEBA2U19 */
-	{0x02d020dd, 1485,  19, INTEL_CYCLONEV}, /* 5CSXFC6D6F31 5CSTFD6D5F31 5CSEBA6U23 5CSEMA6U23 5CSEBA6U19 5CSEBA6U23
-											5CSEBA6U19 5CSEMA6F31 5CSXFC6C6U23 */
-	{0x02b040dd, 1728,  -1, INTEL_CYCLONEV}, /* 5CGXFC9EF35 5CGXBC9AU19 5CGXBC9CF23 5CGTFD9CF23 5CGXFC9AU19 5CGXFC9CF23
-											5CGXFC9EF31 5CGXFC9DF27 5CGXBC9DF27 5CGXBC9EF31 5CGTFD9EF31 5CGTFD9EF35
-											5CGTFD9AU19 5CGXBC9EF35 5CGTFD9DF27 */
-	{0x02b050dd,  864, 163, INTEL_CYCLONEV}, /* 5CEFA4U19 5CEFA4F23 5CEFA4M13 5CEBA4F17 5CEBA4U15 5CEBA4U19 5CEBA4F23 */
-	{0x02b030dd, 1488,  19, INTEL_CYCLONEV}, /* 5CGXBC7CU19 5CGTFD7CU19 5CGTFD7DF27 5CGXFC7BM15 5CGXFC7DF27 5CGXFC7DF31
-											5CGTFD7CF23 5CGXBC7CF23 5CGXBC7DF31 5CGTFD7BM15 5CGXFC7CU19 5CGTFD7DF31
-											5CGXBC7BM15 5CGXFC7CF23 5CGXBC7DF27 */
-	{0x02d120dd, 1485,  -1, INTEL_CYCLONEV}, /* 5CSEBA5U23 5CSEBA5U23 5CSTFD5D5F31 5CSEBA5U19 5CSXFC5D6F31 5CSEMA5U23
-											5CSEMA5F31 5CSXFC5C6U23 5CSEBA5U19 */
-	{0x02b220dd, 1104,  19, INTEL_CYCLONEV}, /* 5CEBA5U19 5CEFA5U19 5CEFA5M13 5CEBA5F23 5CEFA5F23 */
-	{0x02b020dd, 1104,  19, INTEL_CYCLONEV}, /* 5CGXBC5CU19 5CGXFC5F6M11 5CGXFC5CM13 5CGTFD5CF23 5CGXBC5CF23 5CGTFD5CF27
-											5CGTFD5F5M11 5CGXFC5CF27 5CGXFC5CU19 5CGTFD5CM13 5CGXFC5CF23 5CGXBC5CF27
-											5CGTFD5CU19 */
-	{0x02d010dd, 1197,  -1, INTEL_CYCLONEV}, /* 5CSEBA4U23 5CSXFC4C6U23 5CSEMA4U23 5CSEBA4U23 5CSEBA4U19 5CSEBA4U19
-											5CSXFC2C6U23 */
-	{0x02b120dd, 1104,  19, INTEL_CYCLONEV}, /* 5CGXFC4CM13 5CGXFC4CU19 5CGXFC4F6M11 5CGXBC4CU19 5CGXFC4CF27 5CGXBC4CF23
-											5CGXBC4CF27 5CGXFC4CF23 */
-	{0x02b140dd, 1728,  -1, INTEL_CYCLONEV}, /* 5CEFA9F31 5CEBA9F31 5CEFA9F27 5CEBA9U19 5CEBA9F27 5CEFA9U19 5CEBA9F23
-											5CEFA9F23 */
-	{0x02b010dd,  720,  19, INTEL_CYCLONEV}, /* 5CGXFC3U15 5CGXBC3U15 5CGXFC3F23 5CGXFC3U19 5CGXBC3U19 5CGXBC3F23 */
-	{0x02b130dd, 1488,  19, INTEL_CYCLONEV}, /* 5CEFA7F31 5CEBA7F27 5CEBA7M15 5CEFA7U19 5CEBA7F23 5CEFA7F23 5CEFA7F27
-											5CEFA7M15 5CEBA7U19 5CEBA7F31 */
-	{0x02d110dd, 1197,  -1, INTEL_CYCLONEV}, /* 5CSEBA2U23 5CSEMA2U23 5CSEBA2U23 5CSEBA2U19 5CSEBA2U19 */
-
-	{0x020f10dd,  603, 226, INTEL_CYCLONE10}, /* 10CL006E144 10CL006U256 10CL010M164 10CL010U256 10CL010E144 */
-	{0x020f20dd, 1080, 409, INTEL_CYCLONE10}, /* 10CL016U256 10CL016E144 10CL016U484 10CL016F484 10CL016M164 */
-	{0x020f30dd,  732, 286, INTEL_CYCLONE10}, /* 10CL025U256 10CL025E144 */
-	{0x020f40dd, 1632, 604, INTEL_CYCLONE10}, /* 10CL040F484 10CL040U484 */
-	{0x020f50dd, 1164, 442, INTEL_CYCLONE10}, /* 10CL055F484 10CL055U484 */
-	{0x020f60dd, 1314, 502, INTEL_CYCLONE10}, /* 10CL080F484 10CL080F780 10CL080U484 */
-	{0x020f70dd, 1620, 613, INTEL_CYCLONE10}, /* 10CL120F484 10CL120F780 */
-
-	{0x02e120dd, 1339, -1, INTEL_CYCLONE10}, /* 10CX085U484 10CX085F672 */
-	{0x02e320dd, 1339, -1, INTEL_CYCLONE10}, /* 10CX105F780 10CX105U484 10CX105F672 */
-	{0x02e720dd, 1339, -1, INTEL_CYCLONE10}, /* 10CX150F672 10CX150F780 10CX150U484 */
-	{0x02ef20dd, 1339, -1, INTEL_CYCLONE10}, /* 10CX220F672 10CX220F780 10CX220U484 */
-
-	{0x025120dd, 1227, 1174, INTEL_ARRIAII}, /* EP2AGX45 */
-	{0x025020dd, 1227,   -1, INTEL_ARRIAII}, /* EP2AGX65 */
-	{0x025130dd, 1467,   -1, INTEL_ARRIAII}, /* EP2AGX95 */
-	{0x025030dd, 1467,   -1, INTEL_ARRIAII}, /* EP2AGX125 */
-	{0x025140dd, 1971,   -1, INTEL_ARRIAII}, /* EP2AGX190 */
-	{0x025040dd, 1971,   -1, INTEL_ARRIAII}, /* EP2AGX260 */
-	{0x024810dd, 2274,   -1, INTEL_ARRIAII}, /* EP2AGZ225 */
-	{0x0240a0dd, 2682,   -1, INTEL_ARRIAII}, /* EP2AGZ300 */
-	{0x024820dd, 2682,   -1, INTEL_ARRIAII}, /* EP2AGZ350 */
-};
-
-static int intel_fill_device_parameters(struct intel_pld_device *intel_info)
-{
-	for (size_t i = 0; i < ARRAY_SIZE(intel_device_parameters); ++i) {
-		if (intel_device_parameters[i].id == intel_info->tap->idcode &&
-			intel_info->family == intel_device_parameters[i].family) {
-			if (intel_info->boundary_scan_length == 0)
-				intel_info->boundary_scan_length = intel_device_parameters[i].boundary_scan_length;
-
-			if (intel_info->checkpos == -1)
-				intel_info->checkpos = intel_device_parameters[i].checkpos;
-
-			return ERROR_OK;
-		}
-	}
-
-	return ERROR_FAIL;
-}
-
-static int intel_check_for_unique_id(struct intel_pld_device *intel_info)
-{
-	int found = 0;
-	for (size_t i = 0; i < ARRAY_SIZE(intel_device_parameters); ++i) {
-		if (intel_device_parameters[i].id == intel_info->tap->idcode) {
-			++found;
-			intel_info->family = intel_device_parameters[i].family;
-		}
-	}
-
-	return (found == 1) ? ERROR_OK : ERROR_FAIL;
-}
-
 static int intel_check_config(struct intel_pld_device *intel_info)
 {
-	if (!intel_info->tap->has_idcode) {
-		LOG_ERROR("no IDCODE");
-		return ERROR_FAIL;
-	}
-
-	if (intel_info->family == INTEL_UNKNOWN) {
-		if (intel_check_for_unique_id(intel_info) != ERROR_OK) {
-			LOG_ERROR("id is ambiguous, please specify family");
+	if (intel_info->boundary_scan_length == 0) {
+		LOG_ERROR("unknown boundary scan length. Please specify with 'intel set_bscan'.");
 			return ERROR_FAIL;
-		}
-	}
-
-	if (intel_info->boundary_scan_length == 0 || intel_info->checkpos == -1) {
-		int ret = intel_fill_device_parameters(intel_info);
-		if (ret != ERROR_OK)
-			return ret;
 	}
 
 	if (intel_info->checkpos >= 0 && (unsigned int)intel_info->checkpos >= intel_info->boundary_scan_length) {
@@ -305,6 +174,8 @@ static int intel_load(struct pld_device *pld_device, const char *filename)
 			LOG_ERROR("Check failed");
 			return ERROR_FAIL;
 		}
+	} else {
+		LOG_INFO("unable to check. Please specify with position 'intel set_check_pos'.");
 	}
 
 	retval = intel_set_instr(tap, 0x003);
@@ -417,7 +288,7 @@ COMMAND_HANDLER(intel_set_check_pos_command_handler)
 
 PLD_CREATE_COMMAND_HANDLER(intel_pld_create_command)
 {
-	if (CMD_ARGC != 4 && CMD_ARGC != 6)
+	if (CMD_ARGC != 6)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
 	if (strcmp(CMD_ARGV[2], "-chain-position") != 0)
@@ -430,24 +301,23 @@ PLD_CREATE_COMMAND_HANDLER(intel_pld_create_command)
 	}
 
 	enum intel_family_e family = INTEL_UNKNOWN;
-	if (CMD_ARGC == 6) {
-		if (strcmp(CMD_ARGV[4], "-family") != 0)
-			return ERROR_COMMAND_SYNTAX_ERROR;
-
-		if (strcmp(CMD_ARGV[5], "cycloneiii") == 0) {
-			family = INTEL_CYCLONEIII;
-		} else if (strcmp(CMD_ARGV[5], "cycloneiv") == 0) {
-			family = INTEL_CYCLONEIV;
-		} else if (strcmp(CMD_ARGV[5], "cyclonev") == 0) {
-			family = INTEL_CYCLONEV;
-		} else if (strcmp(CMD_ARGV[5], "cyclone10") == 0) {
-			family = INTEL_CYCLONE10;
-		} else if (strcmp(CMD_ARGV[5], "arriaii") == 0) {
-			family = INTEL_ARRIAII;
-		} else {
-			command_print(CMD, "unknown family");
-			return ERROR_FAIL;
-		}
+
+	if (strcmp(CMD_ARGV[4], "-family") != 0)
+		return ERROR_COMMAND_SYNTAX_ERROR;
+
+	if (strcmp(CMD_ARGV[5], "cycloneiii") == 0) {
+		family = INTEL_CYCLONEIII;
+	} else if (strcmp(CMD_ARGV[5], "cycloneiv") == 0) {
+		family = INTEL_CYCLONEIV;
+	} else if (strcmp(CMD_ARGV[5], "cyclonev") == 0) {
+		family = INTEL_CYCLONEV;
+	} else if (strcmp(CMD_ARGV[5], "cyclone10") == 0) {
+		family = INTEL_CYCLONE10;
+	} else if (strcmp(CMD_ARGV[5], "arriaii") == 0) {
+		family = INTEL_ARRIAII;
+	} else {
+		command_print(CMD, "unknown family");
+		return ERROR_FAIL;
 	}
 
 	struct intel_pld_device *intel_info = malloc(sizeof(struct intel_pld_device));
diff --git a/tcl/fpga/altera-arriaii.cfg b/tcl/fpga/altera-arriaii.cfg
index d59c182..9cf680d 100644
--- a/tcl/fpga/altera-arriaii.cfg
+++ b/tcl/fpga/altera-arriaii.cfg
@@ -21,11 +21,26 @@ if { [info exists CHIPNAME] } {
 	set _CHIPNAME arriaii
 }
 
-jtag newtap $_CHIPNAME tap -irlen 10 \
-  -expected-id 0x025120dd -expected-id 0x025040dd \
-  -expected-id 0x025020dd -expected-id 0x024810dd \
-  -expected-id 0x025130dd -expected-id 0x0240a0dd \
-  -expected-id 0x025030dd -expected-id 0x024820dd \
-  -expected-id 0x025140dd
+array set _ARRIA_2_DATA {
+  0x025120dd {1227 1174 EP2AGX45}
+  0x025020dd {1227   -1 EP2AGX65}
+  0x025130dd {1467   -1 EP2AGX95}
+  0x025030dd {1467   -1 EP2AGX125}
+  0x025140dd {1971   -1 EP2AGX190}
+  0x025040dd {1971   -1 EP2AGX260}
+  0x024810dd {2274   -1 EP2AGZ225}
+  0x0240a0dd {2682   -1 EP2AGZ300}
+  0x024820dd {2682   -1 EP2AGZ350}
+}
+
+set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version}
+foreach id [array names _ARRIA_2_DATA] {
+  set cmd [concat "-expected-id" id]
+}
+eval $jtag_newtap_cmd
+
+source [find fpga/altera_common_init.cfg]
 
 pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family arriaii
+jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_ARRIA_2_DATA}"
+
diff --git a/tcl/fpga/altera-cyclone10.cfg b/tcl/fpga/altera-cyclone10.cfg
index 3a1bc1f..0898c74 100644
--- a/tcl/fpga/altera-cyclone10.cfg
+++ b/tcl/fpga/altera-cyclone10.cfg
@@ -4,31 +4,33 @@
 # see: https://www.intel.com/content/www/us/en/docs/programmable/683777/current/bst-operation-control.html
 # and: https://www.intel.cn/content/dam/support/us/en/programmable/kdb/pdfs/literature/hb/cyclone-10/c10gx-51003.pdf
 
-# GX085: 0x02e120dd
-# GX105: 0x02e320dd
-# GX150: 0x02e720dd
-# GX220: 0x02ef20dd
-# 10cl006: 0x020f10dd
-# 10cl010: 0x020f10dd
-# 10cl016: 0x020f20dd
-# 10cl025: 0x020f30dd
-# 10cl040: 0x020f40dd
-# 10cl055: 0x020f50dd
-# 10cl080: 0x020f60dd
-# 10cl120: 0x020f70dd
-
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $CHIPNAME
 } else {
 	set _CHIPNAME cyclone10
 }
 
-jtag newtap $_CHIPNAME tap -irlen 10 \
-  -expected-id 0x02e720dd -expected-id 0x02e120dd \
-  -expected-id 0x02ef20dd -expected-id 0x02e320dd \
-  -expected-id 0x020f10dd -expected-id 0x020f20dd \
-  -expected-id 0x020f30dd -expected-id 0x020f40dd \
-  -expected-id 0x020f50dd -expected-id 0x020f60dd \
-  -expected-id 0x020f70dd
+array set _CYCLONE_10_DATA {
+  0x020f10dd { 603 226 10cl006_10cl010}
+  0x020f20dd {1080 409 10cl016}
+  0x020f30dd { 732 286 10cl025}
+  0x020f40dd {1632 604 10cl040}
+  0x020f50dd {1164 442 10cl055}
+  0x020f60dd {1314 502 10cl080}
+  0x020f70dd {1620 613 10cl120}
+  0x02e120dd {1339  -1 GX085}
+  0x02e320dd {1339  -1 GX105}
+  0x02e720dd {1339  -1 GX150}
+  0x02ef20dd {1339  -1 GX220}
+}
+
+set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version}
+foreach id [array names _CYCLONE_10_DATA] {
+  set cmd [concat "-expected-id" id]
+}
+eval $jtag_newtap_cmd
+
+source [find fpga/altera_common_init.cfg]
 
-pld device intel $_CHIPNAME.tap cyclone10
+pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cyclone10
+jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_10_DATA}"
diff --git a/tcl/fpga/altera-cycloneiii.cfg b/tcl/fpga/altera-cycloneiii.cfg
index d9be645..b0da418 100644
--- a/tcl/fpga/altera-cycloneiii.cfg
+++ b/tcl/fpga/altera-cycloneiii.cfg
@@ -4,32 +4,33 @@
 # see Cyclone III Device Handbook
 # Table 12-2: Device IDCODE for Cyclone III Device Family
 
-#EP3C5     0x020f10dd
-#EP3C10    0x020f10dd
-#EP3C16    0x020f20dd
-#EP3C25    0x020f30dd
-#EP3C40    0x020f40dd
-#EP3C55    0x020f50dd
-#EP3C80    0x020f60dd
-#EP3C120   0x020f70dd
-#Cyclone III LS
-#EP3CLS70  0x027010dd
-#EP3CLS100 0x027000dd
-#EP3CLS150 0x027030dd
-#EP3CLS200 0x027020dd
-
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $CHIPNAME
 } else {
 	set _CHIPNAME cycloneiii
 }
 
-jtag newtap $_CHIPNAME tap -irlen 10 \
-  -expected-id 0x020f10dd -expected-id 0x020f20dd \
-  -expected-id 0x020f30dd -expected-id 0x020f40dd \
-  -expected-id 0x020f50dd -expected-id 0x020f60dd \
-  -expected-id 0x020f70dd -expected-id 0x027010dd \
-  -expected-id 0x027000dd -expected-id 0x027030dd \
-  -expected-id 0x027020dd
+array set _CYCLONE_3_DATA {
+  0x020f10dd { 603 226 EP3C5_EP3C10}
+  0x020f20dd {1080 409 EP3C16}
+  0x020f30dd { 732 286 EP3C25}
+  0x020f40dd {1632 604 EP3C40}
+  0x020f50dd {1164 442 EP3C55}
+  0x020f60dd {1314 502 EP3C80}
+  0x020f70dd {1620 613 EP3C120}
+  0x027010dd {1314 226 EP3CLS70}
+  0x027000dd {1314 226 EP3CLS100}
+  0x027030dd {1314 409 EP3CLS150}
+  0x027020dd {1314 409 EP3CLS200}
+}
+
+set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version}
+foreach id [array names _CYCLONE_3_DATA] {
+  set cmd [concat "-expected-id" id]
+}
+eval $jtag_newtap_cmd
+
+source [find fpga/altera_common_init.cfg]
 
 pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cycloneiii
+jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_3_DATA}"
diff --git a/tcl/fpga/altera-cycloneiv.cfg b/tcl/fpga/altera-cycloneiv.cfg
index 6a908e8..44eb89d 100644
--- a/tcl/fpga/altera-cycloneiv.cfg
+++ b/tcl/fpga/altera-cycloneiv.cfg
@@ -4,38 +4,37 @@
 # see Cyclone IV Device Handbook
 # Table 10-2: IDCODE Information for 32-Bit Cyclone IV Devices
 
-#EP4CE6       0x020f10dd
-#EP4CE10      0x020f10dd
-#EP4CE15      0x020f20dd
-#EP4CE22      0x020f30dd
-#EP4CE30      0x020f40dd
-#EP4CE40      0x020f40dd
-#EP4CE55      0x020f50dd
-#EP4CE75      0x020f60dd
-#EP4CE115     0x020f70dd
-#EP4CGX15     0x028010dd
-#EP4CGX22     0x028120dd
-#EP4CGX30 (3) 0x028020dd
-#EP4CGX30 (4) 0x028230dd
-#EP4CGX50     0x028130dd
-#EP4CGX75     0x028030dd
-#EP4CGX110    0x028140dd
-#EP4CGX150    0x028040dd
-
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $CHIPNAME
 } else {
 	set _CHIPNAME cycloneiv
 }
 
-jtag newtap $_CHIPNAME tap -irlen 10 \
-  -expected-id 0x020f10dd -expected-id 0x020f20dd \
-  -expected-id 0x020f30dd -expected-id 0x020f40dd \
-  -expected-id 0x020f50dd -expected-id 0x020f60dd \
-  -expected-id 0x020f70dd -expected-id 0x028010dd \
-  -expected-id 0x028120dd -expected-id 0x028020dd \
-  -expected-id 0x028230dd -expected-id 0x028130dd \
-  -expected-id 0x028030dd -expected-id 0x028140dd \
-  -expected-id 0x028040dd
+array set _CYCLON_4_DATA {
+  0x020f10dd { 603  226 EP4CE6_EP4CE10}
+  0x020f20dd {1080  409 EP4CE15}
+  0x020f30dd { 732  286 EP4CE22}
+  0x020f40dd {1632  604 EP4CE30_EP4CE40}
+  0x020f50dd {1164  442 EP4CE55}
+  0x020f60dd {1314  502 EP4CE75}
+  0x020f70dd {1620  613 EP4CE115}
+  0x028010dd { 260  229 EP4CGX15}
+  0x028120dd { 494  463 EP4CGX22}
+  0x028020dd { 494  463 EP4CGX30}
+  0x028230dd {1006  943 EP4CGX30}
+  0x028130dd {1006  943 EP4CGX50}
+  0x028030dd {1006  943 EP4CGX75}
+  0x028140dd {1495 1438 EP4CGX110}
+  0x028040dd {1495 1438 EP4CGX150}
+}
+
+set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version}
+foreach id [array names _CYCLON_4_DATA] {
+  set cmd [concat "-expected-id" id]
+}
+eval $jtag_newtap_cmd
+
+source [find fpga/altera_common_init.cfg]
 
 pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cycloneiv
+jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_4_DATA}"
diff --git a/tcl/fpga/altera-cyclonev.cfg b/tcl/fpga/altera-cyclonev.cfg
index 46532a5..8d19cd8 100644
--- a/tcl/fpga/altera-cyclonev.cfg
+++ b/tcl/fpga/altera-cyclonev.cfg
@@ -4,44 +4,36 @@
 # see Cyclone V Device Handbook
 # Table 9-1: IDCODE Information for Cyclone V Devices
 
-#5CEA2 0x02b150dd
-#5CEA4 0x02b050dd
-#5CEA5 0x02b220dd
-#5CEA7 0x02b130dd
-#5CEA9 0x02b140dd
-#5CGXC3 0x02b010dd
-#5CGXC4 0x02b120dd
-#5CGXC5 0x02b020dd
-#5CGXC7 0x02b030dd
-#5CGXC9 0x02b040dd
-#5CGTD5 0x02b020dd
-#5CGTD7 0x02b030dd
-#5CGTD9 0x02b040dd
-#5CSEA2 0x02d110dd
-#5CSEA4 0x02d010dd
-#5CSEA5 0x02d120dd
-#5CSEA6 0x02d020dd
-#5CSXC2 0x02d110dd
-#5CSXC4 0x02d010dd
-#5CSXC5 0x02d120dd
-#5CSXC6 0x02d020dd
-#5CSTD5 0x02d120dd
-#5CSTD6 0x02d020dd
-
-
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $CHIPNAME
 } else {
 	set _CHIPNAME cyclonev
 }
 
-jtag newtap $_CHIPNAME tap -irlen 10 \
-  -expected-id 0x02b150dd -expected-id 0x02b050dd \
-  -expected-id 0x02b220dd -expected-id 0x02b130dd \
-  -expected-id 0x02b140dd -expected-id 0x02b010dd \
-  -expected-id 0x02b120dd -expected-id 0x02b020dd \
-  -expected-id 0x02b030dd -expected-id 0x02b040dd \
-  -expected-id 0x02d110dd -expected-id 0x02d010dd \
-  -expected-id 0x02d120dd -expected-id 0x02d020dd
+array set _CYCLONE_5_DATA {
+  0x02b150dd { 864 163 5CEA2}
+  0x02d020dd {1485  19 5CSEA6_5CSXC6_5CSTD6}
+  0x02b040dd {1728  -1 5CGXC9_5CGTD9}
+  0x02b050dd { 864 163 5CEA4}
+  0x02b030dd {1488  19 5CGXC7_5CGTD7}
+  0x02d120dd {1485  -1 5CSEA5_5CSXC5_5CSTD5}
+  0x02b220dd {1104  19 5CEA5}
+  0x02b020dd {1104  19 5CGXC5_5CGTD5}
+  0x02d010dd {1197  -1 5CSEA4_5CSXC4}
+  0x02b120dd {1104  19 5CGXC4}
+  0x02b140dd {1728  -1 5CEA9}
+  0x02b010dd { 720  19 5CGXC3}
+  0x02b130dd {1488  19 5CEA7}
+  0x02d110dd {1197  -1 5CSEA2_5CSXC2}
+}
+
+set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version}
+foreach id [array names _CYCLONE_5_DATA] {
+  set cmd [concat "-expected-id" id]
+}
+eval $jtag_newtap_cmd
+
+source [find fpga/altera_common_init.cfg]
 
 pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cyclonev
+jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_5_DATA}"
diff --git a/tcl/fpga/altera_common_init.cfg b/tcl/fpga/altera_common_init.cfg
new file mode 100644
index 0000000..683a844
--- /dev/null
+++ b/tcl/fpga/altera_common_init.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+proc set_bscan_checkpos_on_setup {chipname data} {
+  set tapid_w_version [jtag cget $chipname.tap -idcode]
+  set version_mask 0x0fffffff
+  set tapid [format 0x%08x [expr {$tapid_w_version & $version_mask}]]
+  intel set_bscan $chipname.pld [lindex $data($tapid) 0]
+  intel set_check_pos $chipname.pld [lindex $data($tapid) 1]
+}