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2018-06-04Rework/update ARM semihostingLiviu Ionescu13-747/+1895
In 2016, ARM released the second edition of the semihosting specs ("Semihosting for AArch32 and AArch64"), adding support for 64-bits. To ease the reuse of the semihosting logic for other platforms (like RISC-V), the semihosting code was isolated from the ARM target and updated to the latest specs. The new code is already in use since January (in GNU MCU Eclipse OpenOCD) and no problems were reported, neither for ARM nor for RISC-V targets, after more than 7K downloads. The 2 new files were formatted with uncrustify. Change-Id: Ie84dbd86a547323bb8a5d24eab68fc7dad013d96 Signed-off-by: Liviu Ionescu <ilg@livius.net> Reviewed-on: http://openocd.zylin.com/4518 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-05-31jtag: drivers: sysfsgpio: lift upper gpio number limitPaul Fertser1-4/+4
Recent Linux maps GPIOs from 1023 downwards so do not limit the number to 1000. This should fix #183. Change-Id: I6d4f493b670be9ed9b82759f0fb686a9faddbbf5 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4502 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-05-31jtag/drivers: Add support for TI XDS110 debug probeEdward Fewell7-2/+2009
Add support for the XDS110 debug probe using the APIs in the probe's firmware. Includes support for older versions of the firmware (with reduced performance) and support for a newer version that includes OpenOCD specific APIs. Tested on various TI LauchPads including MSP432P4, MSP432E4, CC2650, CC2652, and CC3220SF. Updated to add better support for swd switch. Removed issues found with clang static analysis. Updated to add rules entry for the XDS110 probe and Tiva DFU mode (which affects both XDS110 and ICDI probes). Change-Id: Ib274143111a68e67e80003797c6a68e3e80976b2 Signed-off-by: Edward Fewell <efewell@ti.com> Reviewed-on: http://openocd.zylin.com/4322 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-05-30Fix warnings exposed by GCC8Paul Fertser4-10/+12
gcc (GCC) 8.1.0 generates new warnings and thus fails the build. The ARM disassembler warnings actually exposed a bug in SMALW, SMULW and SMUL instructions decoding. Reported by Eimers on IRC. Change-Id: I200c70f75a9e07a1f13a592addc1c5fb37714440 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4526 Tested-by: jenkins Reviewed-by: Jiri Kastner <cz172638@gmail.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-05-19configure.ac: Fix required libjaylink versionMarc Schink1-1/+1
Change-Id: I9ede86eeef8991db52ffa188ff293c14bd50a1f4 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4450 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-05-09doc: fix several typos within manual documentsAntonio Borneo11-71/+71
Mostly trivial fixes spotted by spell checker Change-Id: I3af693faf5506c866e2abe253a0e37aea3c4d284 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4510 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-27arm_dpm: flush both scratch registers (R0 and R1)Philipp Tomsich1-5/+7
Neither the initial loop to clear dirty registers (which visits all registers starting at R2 and counting upwards) nor the final explicit flushes ensure a write-back in arm_dpm_write_dirty_registers. This change makes sure that both our scratch registers (i.e. R0 and R1) are written back to the target. Change-Id: If65be4f371cd40af9a0cfa97f3730b070b92e981 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-on: http://openocd.zylin.com/4506 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-26doc: fix several typos in openocd.texiAntonio Borneo1-75/+75
Mostly trivial fixes spotted by spell checker One fix s/are/is/ No changes in the content of the document Change-Id: Ic2d8696860c540e901e8c5190f8f1e7dce80545f Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4402 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-04-23ChibiOS thread states: Update thread state to label mappingFaisal Shah1-4/+3
Fixed style issue. Removed #define with list of strings, and just put the strings in the array initialization directly. Removed empty space at the start of line. Change-Id: I76580be203d7d69b8c5b5440f820156543e0d5cc Signed-off-by: Faisal Shah <faisal.shah@gmail.com> Reviewed-on: http://openocd.zylin.com/4488 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-04-23psoc6: Run flash algorithm asynchronously to improve performanceBohdan Tymkiv2-142/+236
Existing psoc6 driver starts flash algorithm for each Flash row. This is suboptimal from performance point of view, starting/stopping flash algorithm for each row adds significant overhead. This change starts flash algorithm and leaves it running asynchronously while driver performs flash operations. Performance gain is 170...250% depending on probe: flash write_image img_256k.bin | w/o this change | with this change | ----------------------------------|-----------------|------------------| KitProg2/CMSIS-DAP, SWD @ 1 MHz | 4 KiB/s | 10 KiB/s | J-Link Ultra, SWD @ 1 MHz | 17 KiB/s | 31 KiB/s | J-Link Ultra, SWD @ 4 MHz | 33 KiB/s | 57 KiB/s | Change-Id: I5bd582584b35af67600c4d197829eb7aeeec7e3f Signed-off-by: Bohdan Tymkiv <bhdt@cypress.com> Reviewed-on: http://openocd.zylin.com/4472 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-04-23flash/nor, contrib/loaders: add stm32 loaders Makefile and generated .incTomas Vanek16-178/+87
Flash loaders refactored to the new style - use generated .inc instead of hexadecimal machine code in the flash driver source. Change-Id: If65a2099589e210f9450819b467d67819fd841fc Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4439 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-23board: add configuration for stm32f103c8 "Blue Pill"Matthias Welwarsky2-1/+23
The "Blue Pill" is a popular development board with an STM32F103C8 micro controller. According to sources, it has a 128kB Flash on board even though the option bytes only report 64kB. This patch therefore also modifies target/stm32f1x.cfg to take an optional FLASH_SIZE variable into account which the board file sets to 0x20000. Change-Id: I8a78ccd2b5faf637c539ee3cf8136789ee15c95d Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4495 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-04-18tcl/target: Add Renesas R-Car R8A7790 H2 targetMarek Vasut1-0/+36
Add configuration for the Renesas R-Car R8A7790 H2 target. This is an SoC with four Cortex A15 and four Cortex A7 ARMv7a cores, only the four A15 cores are supported. Change-Id: I6099b257cc0f04e6858ed5f5f8c8d8ad82ef7650 Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-on: http://openocd.zylin.com/4490 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-17jtag: adapter: fix indentation in handle_interface_commandAntonio Borneo1-8/+8
Minor fix, no code change, just align it to the block it belongs to. Change-Id: I4c3b0d0bd00a55d5109d3723e5c4bfb2fc72e366 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4492 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-12target: add Cortex-M4 target to VF6xx targetMatthias Welwarsky1-1/+1
The Vybrid VF6xx SoCs contain an additional Cortex-M4 core connected to AP number 3 of the main DAP. Change-Id: I59c020fdfc53e909b1f0dac1a8627a62cdaa74f2 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3640 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-12target/cortex_m: allow setting the type of a breakpointTomas Vanek3-32/+5
Cortex-M target used 'auto_bp_type' mode. The requested type of breakpoint was ignored and hard (FPB) breakpoints were set in 'code memory area' 0x00000000-0x1fffffff, soft breakpoints were set above 0x20000000. The code memory area of Cortex-M does not mean the memory is flash and vice versa. External flash (parallel or QSPI) is usually mapped above code memory area. Cortex-M7 ITCM RAM is mapped at 0. Kinetis has a RAM block under 0x20000000 boundary. Remove 'auto_bp_type' mode, set breakpoints to requested type. Change 'cortex_m maskisr auto' handling to use a hard temporary breakpoint everywhere: it can also workaround not working soft breakpoints on Cortex-M7 with ICache enabled. Change-Id: I7a9f9464c5e10bfd7f17cba1037ed07a064fa2e8 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4429 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-10armv8: valgrind memleak fixesMatthias Welwarsky7-9/+74
Various fixes for memory leaks, adds a target cleanup for aarch64 and ARM CTI objects. Change-Id: I2267f0894df655fdf73d70c11ed03df0b8f8d07d Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4478 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-04-10target: add configuration for NXP MC-IMX8M-EVKMatthias Welwarsky2-0/+77
includes target configuration for i.MX8M SoC family, board file needs to set up CHIPNAME and CHIPCORES to match the actual hardware configuration Change-Id: Ieb6d89cab2477a58f85d0ef9cd242710950191c0 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4434 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-10tcl/board: add board configuration for NXP IMX7SABREMatthias Welwarsky1-0/+114
configuration also contains a reset-init procedure that disables the watchdog and initilizes the boards DDR memory so that you can upload baremetal (e.g. boot loader) code into DDR and start it from there. Change-Id: I4d2311b3708a5fcb5174a3447f34ae3904de7243 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4227 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-10flash/nor/at91sam: implement flash bank deallocation for SAM seriesTomas Vanek4-53/+61
Microchip (former Atmel) SAM drivers allocate a struct per chip. at91sam3, at91sam34: Deallocate all chip structs from the list at once, on the first bank deallocation. at91samd and at91sam4l drivers do not handle more than one bank. Convert them to simple driver_priv allocation and use default_flash_free_driver_priv(). Change-Id: I49d7200f38a4568c7e12f306c27d1b1b72646736 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4416 Tested-by: jenkins
2018-04-10flash/nor/kinetis: implement flash bank deallocationTomas Vanek1-1/+18
Change-Id: I8ef80eae646d3b3eb7f6dd42067f8516adc5abef Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4415 Tested-by: jenkins
2018-04-10flash/nor: handle flash write alignment/padding in the infrastructureTomas Vanek3-121/+312
Most of flash drivers have to ensure proper flash write block alignment and padding. As there was no support for it in the flash infrastructure, each driver does it its own way. Sometimes this part of code is not properly tested and contains bugs. flash_write(_unlock) joins all image sections targeted to one flash bank using padded areas as a glue. This solves alignment problems on section boundaries but imposes other problems. Introduce new flash bank parameters write_start_alignment, write_end_alignment and minimal_write_gap. New flash drivers can just properly set these values instead of handling alignment by its own. Adapt infrastructure (namely flash_write_unlock(), handle_flash_fill_command() and handle_flash_write_bank_command()) to prepare write data padded to an alignment required by the flash bank. Rework flash_write_unlock() to discontinue write block when the gap between sections is bigger than minimum specified in minimal_write_gap. minimal_write_gap is set to one sector by default. Change-Id: I4368dd402dfaf51c193bcbf1332cffff092b239b Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4399 Tested-by: jenkins Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
2018-04-10target armv7m: multi-block erase checkTomas Vanek6-98/+137
Tested on PSoC6 (Cortex-M0+ core), onboard KitProg2 in CMSIS-DAP mode, adapter_khz=1000. Plain read: flash read_bank 0 /dev/null takes 48 seconds. erase_check without this change: flash erase_check 0 takes horrible 149 seconds!! And the same command with the change applied takes 1.8 seconds. Quite a difference. Remove the erase-value=0 version of algorithm as the new one can check for any value. If the target is an insane slow clocked CPU (under 1MHz) algo timeouts. Blocks checked so far are returned and the next call uses increased timeout. Change-Id: Ic0899011256d2114112e67c0b51fab4f6230d9cd Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4298 Tested-by: jenkins Reviewed-by: Jonas Norling <jonas.norling@cyanconnode.com> Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
2018-04-10target, flash: prepare infrastructure for multi-block blank checkTomas Vanek12-95/+82
'flash erase_check' command runs a check algorithm on a target if possible. The algorithm is run repeatedly for each flash sector. Unfortunately every start and stop of the algorithm impose not negligible overhead. In practice it means checking is faster than plain read only for sectors of size approx 4 kByte or bigger. And checking sectors as short as 512 bytes runs approx 4 times slower than plain read. The patch changes API call target_blank_check_memory() and related to take an array of sectors (or arbitrary memory blocks). Changes in target-specific checking routines are kept minimal. They use only the first block from the array and process it by the unchanged algorithm. default_flash_blank_check() routine repeats target_blank_check_memory() until all blocks are checked, so it works with both multi-block and single-block based checkers. Change-Id: I0e6c60f2d71364c9c07c09416b04de9268807f5e Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4297 Tested-by: jenkins Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
2018-04-09tcl/target: Add Renesas R-Car R8A7791 M2W targetNiklas Söderlund1-0/+27
Add configuration for the Renesas R-Car R8A7791 M2W target. This is an SoC with two Cortex A15 ARMv7a cores, both cores are supported. This patch is based on initial submission by Adam Bass and improvements by Niklas Söderlund. Change-Id: I297da62b9ce71ad222a401d98e6bcb8502427673 Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Adam Bass <adam.bass@renesas.com> Cc: Niklas Söderlund <niklas.soderlund@ragnatech.se> Reviewed-on: http://openocd.zylin.com/4485 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-09HACKING: document practices to improve code qualityPaul Fertser1-4/+50
Change-Id: I58a7d978b7d5bca3037c4535f06746b9f4411950 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4343 Tested-by: jenkins
2018-04-09configure: disable all drivers when zy1000 is enabledPaul Fertser2-4/+4
This also fixes the transport_is_hla FIXME. Change-Id: I33960f373f11e3e203f9aed9c6d02bf7ca48ac97 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4473 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-04-07gdb_server: gdb_memory_map() reworkTomas Vanek1-17/+21
Use sector sizes instead of bank size. Detect a gap between sectors and emit xml blocks accordingly. Detect sector overflow over the bank size. Change-Id: If0e0e44b0c3b93067b4d717c9c7b07c08582e57b Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4436 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-07rtos: Fix XPSR_OFFSET for cortex_m4f stackingArmin van der Togt1-2/+21
Structures rtos_standard_Cortex_M4F_stacking and rtos_standard_Cortex_M4F_FPU_stacking in rtos_standard_stackings.c where using rtos_standard_Cortex_M3_stack_align for the stack-align function. This function calls rtos_Cortex_M_stack_align with XPSR_OFFSET = 0x3c. This offset is correct for cortex-M3 but not for cortex-M4F and cortex-M4F with fpu. This patch adds stack_align functions for M4F an M4F_FPU Change-Id: If6a90b1898fccbb85619a10f3aef5277dd88ce47 Signed-off-by: Armin van der Togt <armin@otheruse.nl> Reviewed-on: http://openocd.zylin.com/4037 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-04-07target: free target SMP list on shutdownMatthias Welwarsky1-0/+12
On SMP targets, the "target smp" command creates a list of targets that belong to the SMP cluster. Free this list when a target gets destroyed on shutdown. For simplicity, the complete list is free'd as soon as the first target of the SMP cluster is destroyed instead of individually removing targets from the list. Change-Id: Ie217ae1efb2e819c288ff3b1155aeaf0a19b06be Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4481 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-04-07target/arm_adi_v5: extend apcsw command to accept arbitrary bitsTomas Vanek4-21/+75
apcsw command was limited to SPROT bit only. Now user can manipulate any bit except size and addrinc fields. Can be used e.g. to set bus signal 'cacheable' on Cortex-M7 Change-Id: Ia1c22b208e46d1653136f6faa5a7aaab036de7aa Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4431 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-07Add gdb_report_register_access_error commandTim Newsome2-6/+57
With this option enabled (it's disabled by default) errors accessing registers are returned to gdb. Otherwise they are ignored and success is reported to gdb. (This is the current behavior.) We want this for RISC-V, but there's still some cleanup that needs to be done before that can be upstreamed. Signed-off-by: Tim Newsome <tim@sifive.com> Change-Id: I7e56109ea52d18b780c14a07fb35f9e6e8979da4 Reviewed-on: http://openocd.zylin.com/4452 Reviewed-by: Steven Stallion <sstallion@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Tested-by: jenkins
2018-04-07arm_adi_v5: Add ability to ignore the CSYSPWRUPACK bitMatthias Welwarsky5-10/+38
The CTRL/STAT register in the ARM DAP DP has a debug power up ack bit and a system power up ack bit. Some devices do not set the system power up ack bit until sometime later. To avoid having the initial target examination fail due to this or to have a sticky bit error report claim power failure due to this a user can now specify that this bit should be ignored. Change-Id: I2451234bbe904984e29562ef6f616cc6d6f60732 Signed-off-by: Eric Katzfey <eric.katzfey@mentalbee.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3710 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-06flash/nor/at91samd: Add "nvmuserrow" command.Stefan Arnold2-86/+266
Add option "nvmuserrow" to "at91samd" for changing and reading the register at 0x804000 which represents various fuses. Change-Id: I6382cc4ac15e6b9681e2f30b0ae60397a6289c3b Signed-off-by: Stefan Arnold <sarnold@sh-sw.de> Reviewed-on: http://openocd.zylin.com/4260 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-04-04nrf51: Add HWID 0x008F againTomas Vanek1-5/+6
HWID originally added in commit 7829f31a6dd61297e97d8e94fe98a1658eac833e was accidentally omited during refactoring in commit 52885d2b538dcd4184aae14cf2706fb97acccbd9 While on it move old ingeneering sample of 51822 to block of 51822 rev 1 Change-Id: Ie9f15563792a27a72e71df6edbcc6b04490370ed Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4437 Tested-by: jenkins
2018-04-04drivers/kitprog: workaround KitProg firmware bug of missing ZLPTomas Vanek1-3/+13
KitProg firmware does not send a zero length packet at the end of the bulk-in transmission of a length divisible by a bulk packet size. This is inconsistent with the USB specification and results in jtag_libusb_bulk_read() waits forever when a transmission of specific size is received. Limit bulk read size to expected number of bytes for problematic tranfer sizes. Use 1 second timeout as the last resort. Change-Id: Ice80306424afd76e9fbc6851911ffd5109c84501 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4426 Tested-by: jenkins Reviewed-by: Bohdan Tymkiv <bhdt@cypress.com>
2018-04-04target/cortex_m: avoid dwt comparator overflowCody P Schafer1-0/+13
Avoid ever overflowing the DWT_COMPARATOR array by allocating space for 16 comparators (the field is masked by 0xf). On a stm32f767zi chip (on a nucleo-767zi board) I've been seeing crashes with address sanitizer enabled due to its (apparent) 10 present comparators. This appears to be due to https://sourceforge.net/p/openocd/tickets/178/. In non-address sanitizer builds, this would likely cause some random memory to be written to in some cases. (see above bug for observations). Change-Id: I2b7d599eb326236dbc93f74b350c442c9a502c4b Signed-off-by: Cody P Schafer <openocd@codyps.com> Reviewed-on: http://openocd.zylin.com/4458 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-04-04Fix for warnings detected by clang static analyzerMichele Sardo1-0/+5
Fix for potential memory leakage and for unused/unreported return error code Change-Id: Ifb2c95b60637c3a241ad4bf41d1a328c92ccea4b Signed-off-by: Michele Sardo <msmttchr@gmail.com> Reviewed-on: http://openocd.zylin.com/4476 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-04-04flash/nor: implement flash bank deallocation in drivers with simple allocTomas Vanek40-4/+45
All drivers which simply allocate one driver_priv memory block per each bank now use default_flash_free_driver_priv() Change-Id: I425bf4213c3632f02dbe11ab819c31eda9b2db62 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4417 Tested-by: jenkins Reviewed-by: Liviu Dudau <liviu@dudau.co.uk> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-30xilinx-dna.cfg: generic tools for reading Xilinx Device DNARobert Jordens3-0/+45
Most Xilinx FPGA devices contain an embedded, unique device identifier. The identifier is nonvolatile, permanently programmed into the FPGA, and is unchangeable providing a great serial / tracking number. This commit adds generic support for reading the Xilinx Spartan 6 and 7 Series (Kintex, Artix, Ultrascale) Device DNA. The code is similar to the function in fpga/xilinx-xc6s.cfg for Spartan 6 but the register addresses are different and the logic has been simplified. The code was not placed in xilinx-xc7.cfg. The approach of defining taps in the same file as library code to use them is fundamentally broken on boards that have more than one FPGA or other chips. This commit (like the addition of support for Xilinx XADC) starts to remedy that by splitting library code from board-specific fixed definitions. The support code is sourced in the Kasli and KC705 board support files as it was tested on these boards. Change-Id: Iba559c7c1b7e93e1270535fd9e6650007f3794da Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4396 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-30tcl/fpga/xilinx-xadc.cfg: add support for XADCRobert Jordens3-0/+161
The 7 Series FPGAs contain an on-chip 12 bit ADC that can probe die temperature, internal power supply rail voltages as well as external voltages. The XADC is available both from fabric as well as through the JTAG TAP. This code implements access throught the JTAG TAP. https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf Change-Id: I6cef4d0244add71749fa28b58a736302151cc4dd Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4395 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-30jtag/core, target: unregister JTAG eventsTomas Vanek3-2/+12
Also call adapter_exit() before command_exit() as the latter releases Jim interpreter so JTAG events should be released before. Fixes memory leak reported by valgrind Change-Id: I493f3fcba34ea2b4234148e79a4e329c866e0f05 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4474 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-30target: fix display halt message logicTomas Vanek3-5/+8
If a target is run from gdb and then stopped from OpenOCD telnet interface, halt does not show message with status and PC registers. While on it rename 'display' to 'verbose_halt_msg' and use bool type instead of int. Change-Id: Ibe6589015b302e0be97258b06938c297745436a5 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4475 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-30flash/nor: implement flash bank deallocation on OpenOCD exitTomas Vanek4-1/+42
Change-Id: I8fcf09b2a85b3b68743f5fd68a31edea933b9b17 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4414 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-30tcl/board: add support for KasliRobert Jordens1-0/+13
Kasli is an open hardware FPGA board. It is part of the Sinara family of devices designed to control quantum physics experiments (see Sayma_AMC for other boards already suppported by openocd). Kasli was developed as part of the opticlock project. It features a Xilinx Artix 7 100T FPGA, DDR3 RAM, a clock reconstruction and distribution network, four 6 Gb/s transceiver links (three SFP and one SATA) as well as interfaces to up to 12 Eurocard Extension Modules (EEMs). https://github.com/m-labs/sinara/wiki/Kasli http://www.opticlock.de/en/ Change-Id: I88b5e9f16b79e1e731056c45da6b5e1448d2c0e7 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4341 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-30sayma_amc: add Sayma AMC board definitionRobert Jordens1-0/+45
Change-Id: I4a3dc5fe2d81b6906099af8cc1a360b3cf4a6b80 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4237 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-30kcu105: add support for Xilinx KCU105Robert Jordens1-0/+11
* Development board with Kintex Ultrascale XCKU040 * Dual SPI 256 MBit flash, supported through xilinx_bscan_spi Change-Id: I478ec7481beedd270bfba8af56a93301b0ee3028 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4189 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-30xilinx-xcu: add Xilinx Ultrascale tap dataRobert Jordens1-0/+72
The Ultrascale series is a bit more complicated to handle since with the stacked and interconnected dies the IR gets longer. This adds support for all currently known chips from the Ultrascale family. Change-Id: Ibac325dd6fadc76f73cc682b1c62c1a5f39f0786 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4188 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-30target: restructure dap supportMatthias Welwarsky88-493/+1051
- add 'dap create' command to create dap instances - move all dap subcmmand into the dap instance commands - keep 'dap info' for convenience - change all armv7 and armv8 targets to take a dap instance instead of a jtag chain position - restructure tap/dap/target relations, jtag tap no longer references the dap, daps are now independently created and initialized. - clean up swd connect - re-initialize DAP also on JTAG errors (e.g. after reset, power cycle) - update documentation - update target files Change-Id: I322cf3969b5407c25d1d3962f9d9b9bc1df067d9 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4468 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-30tcl/board: add configuration for the avnet ultrazed-eg starter kitMatthias Welwarsky2-0/+106
also contains target configuration for the Xilinx UltraScale+ platform Change-Id: I6300cbc85c1ed71df71d8aaca59500bbf18f0093 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4467 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
generated by cgit v1.1 at 2024-08-18 07:24:27 +0000