diff options
Diffstat (limited to 'tcl')
| -rw-r--r-- | tcl/target/lpc1xxx.cfg | 24 | ||||
| -rw-r--r-- | tcl/target/lpc40xx.cfg | 8 |
2 files changed, 22 insertions, 10 deletions
diff --git a/tcl/target/lpc1xxx.cfg b/tcl/target/lpc1xxx.cfg index 2a2db94..226425d 100644 --- a/tcl/target/lpc1xxx.cfg +++ b/tcl/target/lpc1xxx.cfg @@ -1,4 +1,4 @@ -# Main file for NXP LPC1xxx series Cortex-M0/0+/3 parts +# Main file for NXP LPC1xxx/LPC40xx series Cortex-M0/0+/3/4F parts # # !!!!!! # @@ -11,9 +11,10 @@ # LPC8xx chips support only SWD transport. # LPC11xx chips support only SWD transport. # LPC12xx chips support only SWD transport. -# LPC11Uxx chips support both JTAG and SWD transports. -# LPC13xx chips support both JTAG and SWD transports. +# LPC11Uxx chips support only SWD transports. +# LPC13xx chips support only SWD transports. # LPC17xx chips support both JTAG and SWD transports. +# LPC40xx chips support both JTAG and SWD transports. # Adapt based on what transport is active. source [find target/swj-dp.tcl] @@ -25,7 +26,7 @@ if { [info exists CHIPNAME] } { if { [info exists CHIPSERIES] } { # Validate chip series is supported - if { $CHIPSERIES != "lpc800" && $CHIPSERIES != "lpc1100" && $CHIPSERIES != "lpc1200" && $CHIPSERIES != "lpc1300" && $CHIPSERIES != "lpc1700" } { + if { $CHIPSERIES != "lpc800" && $CHIPSERIES != "lpc1100" && $CHIPSERIES != "lpc1200" && $CHIPSERIES != "lpc1300" && $CHIPSERIES != "lpc1700" && $CHIPSERIES != "lpc4000" } { error "Unsupported LPC1xxx chip series specified." } set _CHIPSERIES $CHIPSERIES @@ -43,10 +44,10 @@ if { [info exists CCLK] } { # Allow user override set _CCLK $CCLK } else { - # LPC8xx/LPC11xx/LPC12xx/LPC13xx use a 12MHz one, LPC17xx uses a 4MHz one + # LPC8xx/LPC11xx/LPC12xx/LPC13xx use a 12MHz one, LPC17xx uses a 4MHz one(except for LPC177x/8x,LPC407x/8x) if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } { set _CCLK 12000 - } elseif { $_CHIPSERIES == "lpc1700" } { + } elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } { set _CCLK 4000 } } @@ -55,10 +56,10 @@ if { [info exists CPUTAPID] } { # Allow user override set _CPUTAPID $CPUTAPID } else { - # LPC8xx/LPC11xx/LPC12xx use a Cortex M0/M0+ core, LPC13xx/LPC17xx use a Cortex M3 core + # LPC8xx/LPC11xx/LPC12xx use a Cortex M0/M0+ core, LPC13xx/LPC17xx use a Cortex M3 core,LPC40xx use a Cortex-M4F core. if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" } { set _CPUTAPID 0x0bb11477 - } elseif { $_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1700" } { + } elseif { $_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } { if { [using_jtag] } { set _CPUTAPID 0x4ba00477 } { @@ -82,7 +83,8 @@ target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME # The LPC12xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000) # The LPC11Uxx devices have 4/6/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000) # The LPC13xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000) -# The LPC17xx devices have 8/16/32kB of SRAM in the ARMv7-M "Code" area (at 0x10000000) +# The LPC17xx devices have 8/16/32/64kB of SRAM in the ARMv7-M "Code" area (at 0x10000000) +# The LPC40xx devices have 16/32/64kB of SRAM in the ARMv7-ME "Code" area (at 0x10000000) $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE # The LPC11xx devies have 8/16/24/32/48/56/64kB of flash memory (at 0x00000000) @@ -90,6 +92,7 @@ $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE # The LPC11Uxx devies have 16/24/32/40/48/64/96/128kB of flash memory (at 0x00000000) # The LPC13xx devies have 8/16/32kB of flash memory (at 0x00000000) # The LPC17xx devies have 32/64/128/256/512kB of flash memory (at 0x00000000) +# The LPC40xx devies have 64/128/256/512kB of flash memory (at 0x00000000) # # All are compatible with the "lpc1700" variant of the LPC2000 flash driver # (same cmd51 destination boundary alignment, and all three support 256 byte @@ -115,7 +118,7 @@ if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "l $_TARGETNAME configure -event reset-init { mww 0x40048000 0x02 } -} elseif { $_CHIPSERIES == "lpc1700" } { +} elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } { # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select # "User Flash Mode" where interrupt vectors are _not_ remapped, # and reside in flash instead). @@ -148,6 +151,7 @@ if {[using_jtag]} { # LPC8xx (Cortex M0+ core) support SYSRESETREQ # LPC11xx/LPC12xx (Cortex M0 core) support SYSRESETREQ # LPC13xx/LPC17xx (Cortex M3 core) support SYSRESETREQ +# LPC40xx (Cortex M4F core) support SYSRESETREQ if {![using_hla]} { # if srst is not fitted use SYSRESETREQ to # perform a soft reset diff --git a/tcl/target/lpc40xx.cfg b/tcl/target/lpc40xx.cfg new file mode 100644 index 0000000..606cda5 --- /dev/null +++ b/tcl/target/lpc40xx.cfg @@ -0,0 +1,8 @@ +# NXP LPC40xx Cortex-M4F with at least 16kB SRAM +set CHIPNAME lpc40xx +set CHIPSERIES lpc4000 +if { ![info exists WORKAREASIZE] } { + set WORKAREASIZE 0x4000 +} + +source [find target/lpc1xxx.cfg] |