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-rw-r--r--doc/openocd.texi7
-rw-r--r--src/flash/nor/lpc2000.c30
-rw-r--r--tcl/target/lpc1xxx.cfg24
-rw-r--r--tcl/target/lpc40xx.cfg8
4 files changed, 52 insertions, 17 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 9adc80f..c708c20 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -5208,7 +5208,7 @@ supported.}
@deffn {Flash Driver} lpc2000
This is the driver to support internal flash of all members of the
LPC11(x)00 and LPC1300 microcontroller families and most members of
-the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4300 and LPC54100
+the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000 and LPC54100
microcontroller families from NXP.
@quotation Note
@@ -5225,15 +5225,16 @@ which must appear in the following order:
@item @var{variant} ... required, may be
@option{lpc2000_v1} (older LPC21xx and LPC22xx)
@option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
-@option{lpc1700} (LPC175x and LPC176x)
+@option{lpc1700} (LPC175x and LPC176x and LPC177x/8x)
@option{lpc4300} - available also as @option{lpc1800} alias (LPC18x[2357] and
LPC43x[2357])
@option{lpc800} (LPC8xx)
@option{lpc1100} (LPC11(x)xx and LPC13xx)
@option{lpc1500} (LPC15xx)
@option{lpc54100} (LPC541xx)
+@option{lpc4000} (LPC40xx)
or @option{auto} - automatically detects flash variant and size for LPC11(x)00,
-LPC8xx, LPC13xx and LPC17xx
+LPC8xx, LPC13xx, LPC17xx and LPC40xx
@item @var{clock_kHz} ... the frequency, in kiloHertz,
at which the core is running
@item @option{calc_checksum} ... optional (but you probably want to provide this!),
diff --git a/src/flash/nor/lpc2000.c b/src/flash/nor/lpc2000.c
index 0b063d3..c2a1fc2 100644
--- a/src/flash/nor/lpc2000.c
+++ b/src/flash/nor/lpc2000.c
@@ -40,7 +40,7 @@
/**
* @file
- * flash programming support for NXP LPC8xx,LPC1xxx,LPC43xx,LP5410x and LPC2xxx devices.
+ * flash programming support for NXP LPC8xx,LPC1xxx,LPC4xxx,LP5410x and LPC2xxx devices.
*
* @todo Provide a way to update CCLK after declaring the flash bank. The value which is correct after chip reset will
* rarely still work right after the clocks switch to use the PLL (e.g. 4MHz --> 100 MHz).
@@ -65,13 +65,20 @@
* lpc1700:
* - 175x
* - 176x (tested with LPC1768)
+ * - 177x
+ * - 178x (tested with LPC1788)
*
- * lpc4300 (also available as lpc1800 - alias)
+ * lpc4000: (lpc1700's alias)
+ * - 407x
+ * - 408x (tested with LPC4088)
+ *
+ * lpc4300: (also available as lpc1800 - alias)
* - 43x2 | 3 | 5 | 7 (tested with LPC4337/LPC4357)
* - 18x2 | 3 | 5 | 7
*
* lpc800:
* - 810 | 1 | 2 (tested with LPC810/LPC811/LPC812)
+ * - 822 | 4 (tested with LPC824)
*
* lpc1100:
* - 11xx
@@ -100,6 +107,10 @@
* - 134x
* - 175x
* - 176x
+ * - 177x
+ * - 178x
+ * - 407x
+ * - 408x
* - 81x
* - 82x
*/
@@ -229,6 +240,12 @@
#define LPC1787 0x281D3747
#define LPC1788 0x281D3F47
+#define LPC4072 0x47011121
+#define LPC4074 0x47011132
+#define LPC4076 0x47191F43
+#define LPC4078 0x47193F47
+#define LPC4088 0x481D3F47
+
#define LPC810_021 0x00008100
#define LPC811_001 0x00008110
#define LPC812_101 0x00008120
@@ -467,7 +484,7 @@ static int lpc2000_build_sector_list(struct flash_bank *bank)
for (int i = 0; i < bank->num_sectors; i++) {
bank->sectors[i].offset = offset;
- /* sectors 0-15 are 4kB-sized, 16 and above are 32kB-sized for LPC17xx devices */
+ /* sectors 0-15 are 4kB-sized, 16 and above are 32kB-sized for LPC17xx/LPC40xx devices */
bank->sectors[i].size = (i < 16) ? 4 * 1024 : 32 * 1024;
offset += bank->sectors[i].size;
bank->sectors[i].is_erased = -1;
@@ -897,7 +914,7 @@ FLASH_BANK_COMMAND_HANDLER(lpc2000_flash_bank_command)
lpc2000_info->variant = lpc2000_v1;
} else if (strcmp(CMD_ARGV[6], "lpc2000_v2") == 0) {
lpc2000_info->variant = lpc2000_v2;
- } else if (strcmp(CMD_ARGV[6], "lpc1700") == 0) {
+ } else if (strcmp(CMD_ARGV[6], "lpc1700") == 0 || strcmp(CMD_ARGV[6], "lpc4000") == 0) {
lpc2000_info->variant = lpc1700;
} else if (strcmp(CMD_ARGV[6], "lpc1800") == 0 || strcmp(CMD_ARGV[6], "lpc4300") == 0) {
lpc2000_info->variant = lpc4300;
@@ -1369,6 +1386,7 @@ static int lpc2000_auto_probe_flash(struct flash_bank *bank)
break;
case LPC1752:
+ case LPC4072:
lpc2000_info->variant = lpc1700;
bank->size = 64 * 1024;
break;
@@ -1395,6 +1413,7 @@ static int lpc2000_auto_probe_flash(struct flash_bank *bank)
case LPC1754:
case LPC1764:
case LPC1774:
+ case LPC4074:
lpc2000_info->variant = lpc1700;
bank->size = 128 * 1024;
break;
@@ -1412,6 +1431,7 @@ static int lpc2000_auto_probe_flash(struct flash_bank *bank)
case LPC1776:
case LPC1785:
case LPC1786:
+ case LPC4076:
lpc2000_info->variant = lpc1700;
bank->size = 256 * 1024;
break;
@@ -1425,6 +1445,8 @@ static int lpc2000_auto_probe_flash(struct flash_bank *bank)
case LPC1778:
case LPC1787:
case LPC1788:
+ case LPC4078:
+ case LPC4088:
lpc2000_info->variant = lpc1700;
bank->size = 512 * 1024;
break;
diff --git a/tcl/target/lpc1xxx.cfg b/tcl/target/lpc1xxx.cfg
index 2a2db94..226425d 100644
--- a/tcl/target/lpc1xxx.cfg
+++ b/tcl/target/lpc1xxx.cfg
@@ -1,4 +1,4 @@
-# Main file for NXP LPC1xxx series Cortex-M0/0+/3 parts
+# Main file for NXP LPC1xxx/LPC40xx series Cortex-M0/0+/3/4F parts
#
# !!!!!!
#
@@ -11,9 +11,10 @@
# LPC8xx chips support only SWD transport.
# LPC11xx chips support only SWD transport.
# LPC12xx chips support only SWD transport.
-# LPC11Uxx chips support both JTAG and SWD transports.
-# LPC13xx chips support both JTAG and SWD transports.
+# LPC11Uxx chips support only SWD transports.
+# LPC13xx chips support only SWD transports.
# LPC17xx chips support both JTAG and SWD transports.
+# LPC40xx chips support both JTAG and SWD transports.
# Adapt based on what transport is active.
source [find target/swj-dp.tcl]
@@ -25,7 +26,7 @@ if { [info exists CHIPNAME] } {
if { [info exists CHIPSERIES] } {
# Validate chip series is supported
- if { $CHIPSERIES != "lpc800" && $CHIPSERIES != "lpc1100" && $CHIPSERIES != "lpc1200" && $CHIPSERIES != "lpc1300" && $CHIPSERIES != "lpc1700" } {
+ if { $CHIPSERIES != "lpc800" && $CHIPSERIES != "lpc1100" && $CHIPSERIES != "lpc1200" && $CHIPSERIES != "lpc1300" && $CHIPSERIES != "lpc1700" && $CHIPSERIES != "lpc4000" } {
error "Unsupported LPC1xxx chip series specified."
}
set _CHIPSERIES $CHIPSERIES
@@ -43,10 +44,10 @@ if { [info exists CCLK] } {
# Allow user override
set _CCLK $CCLK
} else {
- # LPC8xx/LPC11xx/LPC12xx/LPC13xx use a 12MHz one, LPC17xx uses a 4MHz one
+ # LPC8xx/LPC11xx/LPC12xx/LPC13xx use a 12MHz one, LPC17xx uses a 4MHz one(except for LPC177x/8x,LPC407x/8x)
if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } {
set _CCLK 12000
- } elseif { $_CHIPSERIES == "lpc1700" } {
+ } elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
set _CCLK 4000
}
}
@@ -55,10 +56,10 @@ if { [info exists CPUTAPID] } {
# Allow user override
set _CPUTAPID $CPUTAPID
} else {
- # LPC8xx/LPC11xx/LPC12xx use a Cortex M0/M0+ core, LPC13xx/LPC17xx use a Cortex M3 core
+ # LPC8xx/LPC11xx/LPC12xx use a Cortex M0/M0+ core, LPC13xx/LPC17xx use a Cortex M3 core,LPC40xx use a Cortex-M4F core.
if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" } {
set _CPUTAPID 0x0bb11477
- } elseif { $_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1700" } {
+ } elseif { $_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
if { [using_jtag] } {
set _CPUTAPID 0x4ba00477
} {
@@ -82,7 +83,8 @@ target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
# The LPC12xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
# The LPC11Uxx devices have 4/6/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
# The LPC13xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
-# The LPC17xx devices have 8/16/32kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
+# The LPC17xx devices have 8/16/32/64kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
+# The LPC40xx devices have 16/32/64kB of SRAM in the ARMv7-ME "Code" area (at 0x10000000)
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE
# The LPC11xx devies have 8/16/24/32/48/56/64kB of flash memory (at 0x00000000)
@@ -90,6 +92,7 @@ $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE
# The LPC11Uxx devies have 16/24/32/40/48/64/96/128kB of flash memory (at 0x00000000)
# The LPC13xx devies have 8/16/32kB of flash memory (at 0x00000000)
# The LPC17xx devies have 32/64/128/256/512kB of flash memory (at 0x00000000)
+# The LPC40xx devies have 64/128/256/512kB of flash memory (at 0x00000000)
#
# All are compatible with the "lpc1700" variant of the LPC2000 flash driver
# (same cmd51 destination boundary alignment, and all three support 256 byte
@@ -115,7 +118,7 @@ if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "l
$_TARGETNAME configure -event reset-init {
mww 0x40048000 0x02
}
-} elseif { $_CHIPSERIES == "lpc1700" } {
+} elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
# "User Flash Mode" where interrupt vectors are _not_ remapped,
# and reside in flash instead).
@@ -148,6 +151,7 @@ if {[using_jtag]} {
# LPC8xx (Cortex M0+ core) support SYSRESETREQ
# LPC11xx/LPC12xx (Cortex M0 core) support SYSRESETREQ
# LPC13xx/LPC17xx (Cortex M3 core) support SYSRESETREQ
+# LPC40xx (Cortex M4F core) support SYSRESETREQ
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
diff --git a/tcl/target/lpc40xx.cfg b/tcl/target/lpc40xx.cfg
new file mode 100644
index 0000000..606cda5
--- /dev/null
+++ b/tcl/target/lpc40xx.cfg
@@ -0,0 +1,8 @@
+# NXP LPC40xx Cortex-M4F with at least 16kB SRAM
+set CHIPNAME lpc40xx
+set CHIPSERIES lpc4000
+if { ![info exists WORKAREASIZE] } {
+ set WORKAREASIZE 0x4000
+}
+
+source [find target/lpc1xxx.cfg]
generated by cgit v1.1 at 2024-09-27 16:41:53 +0000