diff options
Diffstat (limited to 'tcl/board')
27 files changed, 311 insertions, 296 deletions
diff --git a/tcl/board/arm_evaluator7t.cfg b/tcl/board/arm_evaluator7t.cfg index 96d859c..ef4b782 100644 --- a/tcl/board/arm_evaluator7t.cfg +++ b/tcl/board/arm_evaluator7t.cfg @@ -5,5 +5,5 @@ source [find target/samsung_s3c4510.cfg] # # FIXME: # Add (A) sdram configuration -# Add (B) flash cfi programing configuration +# Add (B) flash cfi programming configuration # diff --git a/tcl/board/at91cap7a-stk-sdram.cfg b/tcl/board/at91cap7a-stk-sdram.cfg index 8395ba3..8a371e0 100644 --- a/tcl/board/at91cap7a-stk-sdram.cfg +++ b/tcl/board/at91cap7a-stk-sdram.cfg @@ -38,7 +38,7 @@ proc peek32 {address} { # Wait for an expression to be true with a timeout proc wait_state {expression} { - for {set i 0} {$i < 1000} {set i [expr $i + 1]} { + for {set i 0} {$i < 1000} {set i [expr {$i + 1}]} { if {[uplevel 1 $expression] == 0} { return } diff --git a/tcl/board/at91sam9261-ek.cfg b/tcl/board/at91sam9261-ek.cfg index 3963e93..1f3de48 100644 --- a/tcl/board/at91sam9261-ek.cfg +++ b/tcl/board/at91sam9261-ek.cfg @@ -29,30 +29,30 @@ proc at91sam9261ek_reset_init { } { ;# set master_pll_div 1 ;# set master_pll_mul 13 - set val [expr $::AT91_WDT_WDV] ;# Counter Value - set val [expr ($val | $::AT91_WDT_WDDIS)] ;# Watchdog Disable - set val [expr ($val | $::AT91_WDT_WDD)] ;# Delta Value - set val [expr ($val | $::AT91_WDT_WDDBGHLT)] ;# Debug Halt - set val [expr ($val | $::AT91_WDT_WDIDLEHLT)] ;# Idle Halt + set val $::AT91_WDT_WDV ;# Counter Value + set val [expr {$val | $::AT91_WDT_WDDIS}] ;# Watchdog Disable + set val [expr {$val | $::AT91_WDT_WDD}] ;# Delta Value + set val [expr {$val | $::AT91_WDT_WDDBGHLT}] ;# Debug Halt + set val [expr {$val | $::AT91_WDT_WDIDLEHLT}] ;# Idle Halt set config(wdt_mr_val) $val ;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash set config(matrix_ebicsa_addr) $::AT91_MATRIX_EBICSA - set config(matrix_ebicsa_val) [expr ($::AT91_MATRIX_DBPUC | $::AT91_MATRIX_CS1A_SDRAMC)] + set config(matrix_ebicsa_val) [expr {$::AT91_MATRIX_DBPUC | $::AT91_MATRIX_CS1A_SDRAMC}] ;# SDRAMC_CR - Configuration register - set val [expr $::AT91_SDRAMC_NC_9] - set val [expr ($val | $::AT91_SDRAMC_NR_13)] - set val [expr ($val | $::AT91_SDRAMC_NB_4)] - set val [expr ($val | $::AT91_SDRAMC_CAS_3)] - set val [expr ($val | $::AT91_SDRAMC_DBW_32)] - set val [expr ($val | (2 << 8))] ;# Write Recovery Delay - set val [expr ($val | (7 << 12))] ;# Row Cycle Delay - set val [expr ($val | (3 << 16))] ;# Row Precharge Delay - set val [expr ($val | (2 << 20))] ;# Row to Column Delay - set val [expr ($val | (5 << 24))] ;# Active to Precharge Delay - set val [expr ($val | (8 << 28))] ;# Exit Self Refresh to Active Delay + set val $::AT91_SDRAMC_NC_9 + set val [expr {$val | $::AT91_SDRAMC_NR_13}] + set val [expr {$val | $::AT91_SDRAMC_NB_4}] + set val [expr {$val | $::AT91_SDRAMC_CAS_3}] + set val [expr {$val | $::AT91_SDRAMC_DBW_32}] + set val [expr {$val | (2 << 8)}] ;# Write Recovery Delay + set val [expr {$val | (7 << 12)}] ;# Row Cycle Delay + set val [expr {$val | (3 << 16)}] ;# Row Precharge Delay + set val [expr {$val | (2 << 20)}] ;# Row to Column Delay + set val [expr {$val | (5 << 24)}] ;# Active to Precharge Delay + set val [expr {$val | (8 << 28)}] ;# Exit Self Refresh to Active Delay set config(sdram_cr_val) $val diff --git a/tcl/board/at91sam9263-ek.cfg b/tcl/board/at91sam9263-ek.cfg index 645b1a7..ab04228 100644 --- a/tcl/board/at91sam9263-ek.cfg +++ b/tcl/board/at91sam9263-ek.cfg @@ -24,11 +24,11 @@ proc at91sam9263ek_reset_init { } { set config(master_pll_div) 14 set config(master_pll_mul) 171 - set val [expr $::AT91_WDT_WDV] ;# Counter Value - set val [expr ($val | $::AT91_WDT_WDDIS)] ;# Watchdog Disable - set val [expr ($val | $::AT91_WDT_WDD)] ;# Delta Value - set val [expr ($val | $::AT91_WDT_WDDBGHLT)] ;# Debug Halt - set val [expr ($val | $::AT91_WDT_WDIDLEHLT)] ;# Idle Halt + set val $::AT91_WDT_WDV ;# Counter Value + set val [expr {$val | $::AT91_WDT_WDDIS}] ;# Watchdog Disable + set val [expr {$val | $::AT91_WDT_WDD}] ;# Delta Value + set val [expr {$val | $::AT91_WDT_WDDBGHLT}] ;# Debug Halt + set val [expr {$val | $::AT91_WDT_WDIDLEHLT}] ;# Idle Halt set config(wdt_mr_val) $val @@ -36,23 +36,23 @@ proc at91sam9263ek_reset_init { } { ;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash set config(matrix_ebicsa_addr) $::AT91_MATRIX_EBI0CSA - set val [expr $::AT91_MATRIX_EBI0_DBPUC] - set val [expr ($val | $::AT91_MATRIX_EBI0_VDDIOMSEL_3_3V)] - set val [expr ($val | $::AT91_MATRIX_EBI0_CS1A_SDRAMC)] + set val $::AT91_MATRIX_EBI0_DBPUC + set val [expr {$val | $::AT91_MATRIX_EBI0_VDDIOMSEL_3_3V}] + set val [expr {$val | $::AT91_MATRIX_EBI0_CS1A_SDRAMC}] set config(matrix_ebicsa_val) $val ;# SDRAMC_CR - Configuration register - set val [expr $::AT91_SDRAMC_NC_9] - set val [expr ($val | $::AT91_SDRAMC_NR_13)] - set val [expr ($val | $::AT91_SDRAMC_NB_4)] - set val [expr ($val | $::AT91_SDRAMC_CAS_3)] - set val [expr ($val | $::AT91_SDRAMC_DBW_32)] - set val [expr ($val | (1 << 8))] ;# Write Recovery Delay - set val [expr ($val | (7 << 12))] ;# Row Cycle Delay - set val [expr ($val | (2 << 16))] ;# Row Precharge Delay - set val [expr ($val | (2 << 20))] ;# Row to Column Delay - set val [expr ($val | (5 << 24))] ;# Active to Precharge Delay - set val [expr ($val | (1 << 28))] ;# Exit Self Refresh to Active Delay + set val $::AT91_SDRAMC_NC_9 + set val [expr {$val | $::AT91_SDRAMC_NR_13}] + set val [expr {$val | $::AT91_SDRAMC_NB_4}] + set val [expr {$val | $::AT91_SDRAMC_CAS_3}] + set val [expr {$val | $::AT91_SDRAMC_DBW_32}] + set val [expr {$val | (1 << 8)}] ;# Write Recovery Delay + set val [expr {$val | (7 << 12)}] ;# Row Cycle Delay + set val [expr {$val | (2 << 16)}] ;# Row Precharge Delay + set val [expr {$val | (2 << 20)}] ;# Row to Column Delay + set val [expr {$val | (5 << 24)}] ;# Active to Precharge Delay + set val [expr {$val | (1 << 28)}] ;# Exit Self Refresh to Active Delay set config(sdram_cr_val) $val diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg index 03296c5..e1cbb91 100644 --- a/tcl/board/at91sam9g20-ek.cfg +++ b/tcl/board/at91sam9g20-ek.cfg @@ -77,25 +77,25 @@ proc at91sam9g20_reset_init { } { # Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR. mww 0xfffffc20 0x00004001 - while { [expr [read_register 0xfffffc68] & 0x01] != 1 } { sleep 1 } + while { [expr {[read_register 0xfffffc68] & 0x01}] != 1 } { sleep 1 } # Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43). # Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable. mww 0xfffffc28 0x202a3f01 - while { [expr [read_register 0xfffffc68] & 0x02] != 2 } { sleep 1 } + while { [expr {[read_register 0xfffffc68] & 0x02}] != 2 } { sleep 1 } # Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR. # Wait for MCKRDY signal from PMC_SR to assert. mww 0xfffffc30 0x00000101 - while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 } + while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 } # Now change PMC_MCKR register to select PLLA. # Wait for MCKRDY signal from PMC_SR to assert. mww 0xfffffc30 0x00001302 - while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 } + while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 } # Processor and master clocks are now operating and stable at maximum frequency possible: # -> MCLK = 132.096 MHz @@ -153,7 +153,7 @@ proc at91sam9g20_reset_init { } { nand probe nandflash_cs3 - # The AT91SAM9G20-EK evaluation board has build-in serial data flash also. + # The AT91SAM9G20-EK evaluation board has built-in serial data flash also. # Now setup SDRAM. This is tricky and configuration is very important for reliability! The current calculations # are based on 2 x Micron MT48LC16M16A2-75 memory (4 M x 16 bit x 4 banks). If you use this file as a reference diff --git a/tcl/board/digilent_atlys.cfg b/tcl/board/digilent_atlys.cfg index f298e3d..3eb6219 100644 --- a/tcl/board/digilent_atlys.cfg +++ b/tcl/board/digilent_atlys.cfg @@ -5,7 +5,7 @@ # ID 1443:0007 Digilent Development board JTAG # # However, the ixo-usb-jtag project provides an alternative open firmware for -# the on board programmer. When using thie firmware the board will then +# the on board programmer. When using this firmware the board will then # enumerate as: # ID 16c0:06ad Van Ooijen Technische Informatica # (With SerialNumber == hw_nexys) diff --git a/tcl/board/dm355evm.cfg b/tcl/board/dm355evm.cfg index 0c971e9..bf5659c 100644 --- a/tcl/board/dm355evm.cfg +++ b/tcl/board/dm355evm.cfg @@ -80,14 +80,14 @@ proc dm355evm_init {} { # VTPIOCR impedance calibration set addr [dict get $dm355 sysbase] - set addr [expr $addr + 0x70] + set addr [expr {$addr + 0x70}] # clear CLR, LOCK, PWRDN; wait a clock; set CLR mmw $addr 0 0x20c0 mmw $addr 0x2000 0 # wait for READY - while { [expr [mrw $addr] & 0x8000] == 0 } { sleep 1 } + while { [expr {[mrw $addr] & 0x8000}] == 0 } { sleep 1 } # set IO_READY; then LOCK and PWRSAVE; then PWRDN mmw $addr 0x4000 0 @@ -108,24 +108,24 @@ proc dm355evm_init {} { set addr [dict get $dm355 ddr_emif] # DDRPHYCR1 - mww [expr $addr + 0xe4] 0x50006404 + mww [expr {$addr + 0xe4}] 0x50006404 # PBBPR -- burst priority - mww [expr $addr + 0x20] 0xfe + mww [expr {$addr + 0x20}] 0xfe # SDCR -- unlock boot config; init for DDR2, relock, unlock SDTIM* - mmw [expr $addr + 0x08] 0x00800000 0 - mmw [expr $addr + 0x08] 0x0013c632 0x03870fff + mmw [expr {$addr + 0x08}] 0x00800000 0 + mmw [expr {$addr + 0x08}] 0x0013c632 0x03870fff # SDTIMR0, SDTIMR1 - mww [expr $addr + 0x10] 0x2a923249 - mww [expr $addr + 0x14] 0x4c17c763 + mww [expr {$addr + 0x10}] 0x2a923249 + mww [expr {$addr + 0x14}] 0x4c17c763 # SDCR -- relock SDTIM* - mmw [expr $addr + 0x08] 0 0x00008000 + mmw [expr {$addr + 0x08}] 0 0x00008000 # SDRCR -- refresh rate (171 MHz * 7.8usec) - mww [expr $addr + 0x0c] 1336 + mww [expr {$addr + 0x0c}] 1336 ######################## # ASYNC EMIF @@ -138,13 +138,13 @@ proc dm355evm_init {} { #set nand_timings 0x0400008c # AWCCR - mww [expr $addr + 0x04] 0xff + mww [expr {$addr + 0x04}] 0xff # CS0 == socketed NAND (default MT29F16G08FAA, 2GByte) - mww [expr $addr + 0x10] $nand_timings + mww [expr {$addr + 0x10}] $nand_timings # CS1 == dm9000 Ethernet - mww [expr $addr + 0x14] 0x00a00505 + mww [expr {$addr + 0x14}] 0x00a00505 # NANDFCR -- only CS0 has NAND - mww [expr $addr + 0x60] 0x01 + mww [expr {$addr + 0x60}] 0x01 # default: both chipselects to the NAND socket are used nand probe 0 @@ -156,27 +156,27 @@ proc dm355evm_init {} { set addr [dict get $dm355 uart0] # PWREMU_MGNT -- rx + tx in reset - mww [expr $addr + 0x30] 0 + mww [expr {$addr + 0x30}] 0 # DLL, DLH -- 115200 baud - mwb [expr $addr + 0x20] 0x0d - mwb [expr $addr + 0x24] 0x00 + mwb [expr {$addr + 0x20}] 0x0d + mwb [expr {$addr + 0x24}] 0x00 # FCR - clear and disable FIFOs - mwb [expr $addr + 0x08] 0x07 - mwb [expr $addr + 0x08] 0x00 + mwb [expr {$addr + 0x08}] 0x07 + mwb [expr {$addr + 0x08}] 0x00 # IER - disable IRQs - mwb [expr $addr + 0x04] 0x00 + mwb [expr {$addr + 0x04}] 0x00 # LCR - 8-N-1 - mwb [expr $addr + 0x0c] 0x03 + mwb [expr {$addr + 0x0c}] 0x03 # MCR - no flow control or loopback - mwb [expr $addr + 0x10] 0x00 + mwb [expr {$addr + 0x10}] 0x00 # PWREMU_MGNT -- rx + tx normal, free running during JTAG halt - mww [expr $addr + 0x30] 0xe001 + mww [expr {$addr + 0x30}] 0xe001 ######################## diff --git a/tcl/board/dm365evm.cfg b/tcl/board/dm365evm.cfg index 3b29dd8..8c7f8c0 100644 --- a/tcl/board/dm365evm.cfg +++ b/tcl/board/dm365evm.cfg @@ -56,10 +56,10 @@ if { $CS0 == "NAND" } { #set nand_timings 0x0400008c # CS0 == socketed NAND (default MT29F16G08FAA, 2 GBytes) - mww [expr $a_emif + 0x10] $nand_timings + mww [expr {$a_emif + 0x10}] $nand_timings # NANDFCR -- CS0 has NAND - mww [expr $a_emif + 0x60] 0x01 + mww [expr {$a_emif + 0x60}] 0x01 } proc flashprobe {} { nand probe 0 @@ -80,10 +80,10 @@ if { $CS0 == "NAND" } { davinci_pinmux $dm365 2 0x00000055 # CS0 == OneNAND (KFG1G16U2B-DIB6, 128 KBytes) - mww [expr $a_emif + 0x10] 0x00000001 + mww [expr {$a_emif + 0x10}] 0x00000001 # ONENANDCTRL -- CS0 has OneNAND, enable sync reads - mww [expr $a_emif + 0x5c] 0x0441 + mww [expr {$a_emif + 0x5c}] 0x0441 } proc flashprobe {} { } } @@ -133,11 +133,11 @@ proc dm365evm_init {} { set a_emif [dict get $dm365 a_emif] # AWCCR - mww [expr $a_emif + 0x04] 0xff + mww [expr {$a_emif + 0x04}] 0xff # CS0 == NAND or OneNAND cs0_setup $a_emif # CS1 == CPLD - mww [expr $a_emif + 0x14] 0x00a00505 + mww [expr {$a_emif + 0x14}] 0x00a00505 # FIXME setup UART0 diff --git a/tcl/board/dp_busblaster_v4.cfg b/tcl/board/dp_busblaster_v4.cfg index 066b54f..7b3bee8 100644 --- a/tcl/board/dp_busblaster_v4.cfg +++ b/tcl/board/dp_busblaster_v4.cfg @@ -10,7 +10,7 @@ # https://raw.githubusercontent.com/dergraaf/busblaster_v4/master/ktlink/ktlink.svf # # To reprogram the on-board CPLD do: -# openocd -f board/dp_busblaster_v4.cfg -c "adapter_khz 1000; init; svf <path_to_svf>; shutdown" +# openocd -f board/dp_busblaster_v4.cfg -c "adapter speed 1000; init; svf <path_to_svf>; shutdown" # source [find interface/ftdi/dp_busblaster.cfg] diff --git a/tcl/board/embedded-artists_lpc2478-32.cfg b/tcl/board/embedded-artists_lpc2478-32.cfg index 8ef9179..38f5e1b 100644 --- a/tcl/board/embedded-artists_lpc2478-32.cfg +++ b/tcl/board/embedded-artists_lpc2478-32.cfg @@ -26,7 +26,7 @@ proc init_board {} { global _CHIPNAME # A working area will help speeding the flash programming - $_TARGETNAME configure -work-area-phys 0x40000200 -work-area-size [expr 0x10000-0x200-0x20] -work-area-backup 0 + $_TARGETNAME configure -work-area-phys 0x40000200 -work-area-size [expr {0x10000-0x200-0x20}] -work-area-backup 0 # External 16-bit flash at chip select CS0 (SST39VF3201-70, 4 MiB) flash bank $_CHIPNAME.extflash cfi 0x80000000 0x400000 2 2 $_TARGETNAME jedec_probe @@ -125,7 +125,7 @@ proc init_board {} { # proc enable_pll {} { # Disconnect PLL in case it is already connected - if {[expr [read_register 0xE01FC080] & 0x03] == 3} { + if {[expr {[read_register 0xE01FC080] & 0x03}] == 3} { # Disconnect it, but leave it enabled # (This MUST be done in two steps) mww 0xE01FC080 0x00000001 ;# PLLCON: disconnect PLL diff --git a/tcl/board/hilscher_nxhx10.cfg b/tcl/board/hilscher_nxhx10.cfg index add424d..1875dac 100644 --- a/tcl/board/hilscher_nxhx10.cfg +++ b/tcl/board/hilscher_nxhx10.cfg @@ -34,7 +34,7 @@ proc mread32 {addr} { proc init_clocks { } { puts "Enabling all clocks " set accesskey [mread32 0x101c0070] - mww 0x101c0070 [expr $accesskey] + mww 0x101c0070 $accesskey mww 0x101c0028 0x00007511 } @@ -42,7 +42,7 @@ proc init_clocks { } { proc init_sdrambus { } { puts "Initializing external SDRAM Bus 16 Bit " set accesskey [mread32 0x101c0070] - mww 0x101c0070 [expr $accesskey] + mww 0x101c0070 $accesskey mww 0x101c0C40 0x00000050 puts "Configuring SDRAM controller for K4S561632E (32MB) " diff --git a/tcl/board/hitex_lpc2929.cfg b/tcl/board/hitex_lpc2929.cfg index 2fe1f3c..8268306 100644 --- a/tcl/board/hitex_lpc2929.cfg +++ b/tcl/board/hitex_lpc2929.cfg @@ -34,7 +34,7 @@ flash bank $_FLASHNAME cfi 0x5C000000 0x400000 2 2 $_TARGETNAME jedec_probe $_TARGETNAME configure -event reset-init { # Flash - mww 0x20200010 0x00000007 ;# FBWST: 7 wait states, not chached + mww 0x20200010 0x00000007 ;# FBWST: 7 wait states, not cached # Use PLL mww 0xFFFF8020 0x00000001 ;# XTAL_OSC_CONTROL: enable, 1-20 MHz diff --git a/tcl/board/icnova_imx53_sodimm.cfg b/tcl/board/icnova_imx53_sodimm.cfg index af98188..363d7b4 100644 --- a/tcl/board/icnova_imx53_sodimm.cfg +++ b/tcl/board/icnova_imx53_sodimm.cfg @@ -45,7 +45,7 @@ proc sodimm_init { } { ; # ARM errata ID #468414 set tR [arm mrc 15 0 1 0 1] - arm mcr 15 0 1 0 1 [expr $tR | (1<<5)] ; # enable L1NEON bit + arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}] ; # enable L1NEON bit init_l2cc init_aips @@ -69,7 +69,7 @@ proc init_l2cc { } { set tR [arm mrc 15 0 1 0 1] ; #bic r0, r0, #0x2 ; #mcr 15, 0, r0, c1, c0, 1 - arm mcr 15 0 1 0 1 [expr $tR & ~(1<<2)] + arm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}] ; #/* reconfigure L2 cache aux control reg */ ; #mov r0, #0xC0 /* tag RAM */ @@ -79,7 +79,7 @@ proc init_l2cc { } { ; #orr r0, r0, #(1 << 22) /* disable write allocate */ ; #mcr 15, 1, r0, c9, c0, 2 - arm mcr 15 1 9 0 2 [expr 0xC4 | (1<<24) | (1<<23) | (1<<22)] + arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}] } @@ -93,10 +93,10 @@ proc init_aips { } { set VAL 0x77777777 # dap apsel 1 - mww [expr $AIPS1_BASE_ADDR + 0x0] $VAL - mww [expr $AIPS1_BASE_ADDR + 0x4] $VAL - mww [expr $AIPS2_BASE_ADDR + 0x0] $VAL - mww [expr $AIPS2_BASE_ADDR + 0x4] $VAL + mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL + mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL + mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL + mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL # dap apsel 0 } @@ -104,22 +104,22 @@ proc init_aips { } { proc init_clock { } { global AIPS1_BASE_ADDR global AIPS2_BASE_ADDR - set CCM_BASE_ADDR [expr $AIPS1_BASE_ADDR + 0x000D4000] + set CCM_BASE_ADDR [expr {$AIPS1_BASE_ADDR + 0x000D4000}] set CLKCTL_CCSR 0x0C set CLKCTL_CBCDR 0x14 set CLKCTL_CBCMR 0x18 - set PLL1_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00080000] - set PLL2_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00084000] - set PLL3_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00088000] - set PLL4_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x0008C000] + set PLL1_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00080000}] + set PLL2_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00084000}] + set PLL3_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00088000}] + set PLL4_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x0008C000}] set CLKCTL_CSCMR1 0x1C set CLKCTL_CDHIPR 0x48 - set PLATFORM_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x000A0000] + set PLATFORM_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x000A0000}] set CLKCTL_CSCDR1 0x24 set CLKCTL_CCDR 0x04 ; # Switch ARM to step clock - mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x4 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4 return echo "not returned" @@ -127,52 +127,52 @@ proc init_clock { } { setup_pll $PLL3_BASE_ADDR 400 ; # Switch peripheral to PLL3 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00015154 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x02888945 | (1<<16)] - while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 } + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}] + while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 } setup_pll $PLL2_BASE_ADDR 400 ; # Switch peripheral to PLL2 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x00808145 | (2<<10) | (9<<16) | (1<<19)] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}] - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00016154 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154 ; # change uart clk parent to pll2 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1]] & 0xfcffffff | 0x01000000] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}] ; # make sure change is effective - while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 } + while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 } setup_pll $PLL3_BASE_ADDR 216 setup_pll $PLL4_BASE_ADDR 455 ; # Set the platform clock dividers - mww [expr $PLATFORM_BASE_ADDR + 0x14] 0x00000124 + mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124 - mww [expr $CCM_BASE_ADDR + 0x10] 0 + mww [expr {$CCM_BASE_ADDR + 0x10}] 0 ; # Switch ARM back to PLL 1. - mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x0 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0 ; # make uart div=6 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1]] & 0xffffffc0 | 0x0a] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}] ; # Restore the default values in the Gate registers - mww [expr $CCM_BASE_ADDR + 0x68] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x6C] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x70] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x74] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x78] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x7C] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x80] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x84] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + $CLKCTL_CCDR] 0x00000 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000 ; # for cko - for ARM div by 8 - mww [expr $CCM_BASE_ADDR + 0x60] [expr 0x000A0000 & 0x00000F0] + mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}] } @@ -187,68 +187,68 @@ proc setup_pll { PLL_ADDR CLK } { set PLL_DP_HFS_MFN 0x24 if {$CLK == 1000} { - set DP_OP [expr (10 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (12 - 1)] + set DP_OP [expr {(10 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {12 - 1}] set DP_MFN 5 } elseif {$CLK == 850} { - set DP_OP [expr (8 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (48 - 1)] + set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {48 - 1}] set DP_MFN 41 } elseif {$CLK == 800} { - set DP_OP [expr (8 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (3 - 1)] + set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {3 - 1}] set DP_MFN 1 } elseif {$CLK == 700} { - set DP_OP [expr (7 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (24 - 1)] + set DP_OP [expr {(7 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {24 - 1}] set DP_MFN 7 } elseif {$CLK == 600} { - set DP_OP [expr (6 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (4 - 1)] + set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {4 - 1}] set DP_MFN 1 } elseif {$CLK == 665} { - set DP_OP [expr (6 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (96 - 1)] + set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {96 - 1}] set DP_MFN 89 } elseif {$CLK == 532} { - set DP_OP [expr (5 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (24 - 1)] + set DP_OP [expr {(5 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {24 - 1}] set DP_MFN 13 } elseif {$CLK == 455} { - set DP_OP [expr (8 << 4) + ((2 - 1) << 0)] - set DP_MFD [expr (48 - 1)] + set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}] + set DP_MFD [expr {48 - 1}] set DP_MFN 71 } elseif {$CLK == 400} { - set DP_OP [expr (8 << 4) + ((2 - 1) << 0)] - set DP_MFD [expr (3 - 1)] + set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}] + set DP_MFD [expr {3 - 1}] set DP_MFN 1 } elseif {$CLK == 216} { - set DP_OP [expr (6 << 4) + ((3 - 1) << 0)] - set DP_MFD [expr (4 - 1)] + set DP_OP [expr {(6 << 4) + ((3 - 1) << 0)}] + set DP_MFD [expr {4 - 1}] set DP_MFN 3 } else { error "Error (setup_dll): clock not found!" } - mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232 - mww [expr $PLL_ADDR + $PLL_DP_CONFIG] 0x2 + mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232 + mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2 - mww [expr $PLL_ADDR + $PLL_DP_OP] $DP_OP - mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_OP + mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP - mww [expr $PLL_ADDR + $PLL_DP_MFD] $DP_MFD - mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_MFD + mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD - mww [expr $PLL_ADDR + $PLL_DP_MFN] $DP_MFN - mww [expr $PLL_ADDR + $PLL_DP_HFS_MFN] $DP_MFN + mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN - mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232 - while {[expr [mrw [expr $PLL_ADDR + $PLL_DP_CTL]] & 0x1] == 0} { sleep 1 } + mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232 + while {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 } } proc CPU_2_BE_32 { L } { - return [expr (($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)] + return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)}] } diff --git a/tcl/board/icnova_sam9g45_sodimm.cfg b/tcl/board/icnova_sam9g45_sodimm.cfg index 30dc347..8a0736b 100644 --- a/tcl/board/icnova_sam9g45_sodimm.cfg +++ b/tcl/board/icnova_sam9g45_sodimm.cfg @@ -89,27 +89,27 @@ proc at91sam9g45_init { } { # Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR. mww 0xfffffc20 0x00004001 - while { [expr [read_register 0xfffffc68] & 0x01] != 1 } { sleep 1 } + while { [expr {[read_register 0xfffffc68] & 0x01}] != 1 } { sleep 1 } # Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43). # Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable. #mww 0xfffffc28 0x202a3f01 mww 0xfffffc28 0x20c73f03 - while { [expr [read_register 0xfffffc68] & 0x02] != 2 } { sleep 1 } + while { [expr {[read_register 0xfffffc68] & 0x02}] != 2 } { sleep 1 } # Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR. # Wait for MCKRDY signal from PMC_SR to assert. #mww 0xfffffc30 0x00000101 mww 0xfffffc30 0x00001301 - while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 } + while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 } # Now change PMC_MCKR register to select PLLA. # Wait for MCKRDY signal from PMC_SR to assert. mww 0xfffffc30 0x00001302 - while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 } + while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 } # Processor and master clocks are now operating and stable at maximum frequency possible: # -> MCLK = 132.096 MHz @@ -214,7 +214,7 @@ proc at91sam9g45_init { } { sleep 1 # 9. Enable DLL Reset (set DLL bit) - set CR [expr [read_register 0xffffe608] | 0x80] + set CR [expr {[read_register 0xffffe608] | 0x80}] mww 0xffffe608 $CR # 10. mode register cycle to reset the DLL @@ -236,7 +236,7 @@ proc at91sam9g45_init { } { # 12.3 delay 10 cycles # 13. disable DLL reset (clear DLL bit) - set CR [expr [read_register 0xffffe608] & 0xffffff7f] + set CR [expr {[read_register 0xffffe608] & 0xffffff7f}] mww 0xffffe608 $CR # 14. mode register set cycle @@ -244,7 +244,7 @@ proc at91sam9g45_init { } { mww 0x70000000 0x1 # 15. program OCD field (set OCD bits) - set CR [expr [read_register 0xffffe608] | 0x7000] + set CR [expr {[read_register 0xffffe608] | 0x7000}] mww 0xffffe608 $CR # 16. (EMRS1) @@ -253,7 +253,7 @@ proc at91sam9g45_init { } { # 16.1 delay 2 cycles # 17. disable OCD field (clear OCD bits) - set CR [expr [read_register 0xffffe608] & 0xffff8fff] + set CR [expr {[read_register 0xffffe608] & 0xffff8fff}] mww 0xffffe608 $CR # 18. (EMRS1) diff --git a/tcl/board/imx31pdk.cfg b/tcl/board/imx31pdk.cfg index 2dce157..6c19654 100644 --- a/tcl/board/imx31pdk.cfg +++ b/tcl/board/imx31pdk.cfg @@ -6,7 +6,7 @@ $_TARGETNAME configure -event reset-init { imx31pdk_init } proc self_test {} { echo "Running 100 iterations of test." dump_image /ram/test 0x80000000 0x40000 - for {set i 0} {$i < 100} {set i [expr $i+1]} { + for {set i 0} {$i < 100} {set i [expr {$i+1}]} { echo "Iteration $i" reset init mww 0x80000000 0x12345678 0x10000 diff --git a/tcl/board/imx53-m53evk.cfg b/tcl/board/imx53-m53evk.cfg index b529c49..04f0f9f 100644 --- a/tcl/board/imx53-m53evk.cfg +++ b/tcl/board/imx53-m53evk.cfg @@ -44,7 +44,7 @@ proc m53evk_init { } { ; # ARM errata ID #468414 set tR [arm mrc 15 0 1 0 1] - arm mcr 15 0 1 0 1 [expr $tR | (1<<5)] ; # enable L1NEON bit + arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}] ; # enable L1NEON bit init_l2cc init_aips @@ -65,7 +65,7 @@ proc init_l2cc { } { set tR [arm mrc 15 0 1 0 1] ; #bic r0, r0, #0x2 ; #mcr 15, 0, r0, c1, c0, 1 - arm mcr 15 0 1 0 1 [expr $tR & ~(1<<2)] + arm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}] ; #/* reconfigure L2 cache aux control reg */ ; #mov r0, #0xC0 /* tag RAM */ @@ -75,7 +75,7 @@ proc init_l2cc { } { ; #orr r0, r0, #(1 << 22) /* disable write allocate */ ; #mcr 15, 1, r0, c9, c0, 2 - arm mcr 15 1 9 0 2 [expr 0xC4 | (1<<24) | (1<<23) | (1<<22)] + arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}] } @@ -89,10 +89,10 @@ proc init_aips { } { set VAL 0x77777777 # dap apsel 1 - mww [expr $AIPS1_BASE_ADDR + 0x0] $VAL - mww [expr $AIPS1_BASE_ADDR + 0x4] $VAL - mww [expr $AIPS2_BASE_ADDR + 0x0] $VAL - mww [expr $AIPS2_BASE_ADDR + 0x4] $VAL + mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL + mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL + mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL + mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL # dap apsel 0 } @@ -100,22 +100,22 @@ proc init_aips { } { proc init_clock { } { global AIPS1_BASE_ADDR global AIPS2_BASE_ADDR - set CCM_BASE_ADDR [expr $AIPS1_BASE_ADDR + 0x000D4000] + set CCM_BASE_ADDR [expr {$AIPS1_BASE_ADDR + 0x000D4000}] set CLKCTL_CCSR 0x0C set CLKCTL_CBCDR 0x14 set CLKCTL_CBCMR 0x18 - set PLL1_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00080000] - set PLL2_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00084000] - set PLL3_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00088000] - set PLL4_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x0008C000] + set PLL1_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00080000}] + set PLL2_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00084000}] + set PLL3_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00088000}] + set PLL4_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x0008C000}] set CLKCTL_CSCMR1 0x1C set CLKCTL_CDHIPR 0x48 - set PLATFORM_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x000A0000] + set PLATFORM_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x000A0000}] set CLKCTL_CSCDR1 0x24 set CLKCTL_CCDR 0x04 ; # Switch ARM to step clock - mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x4 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4 return echo "not returned" @@ -123,52 +123,52 @@ proc init_clock { } { setup_pll $PLL3_BASE_ADDR 400 ; # Switch peripheral to PLL3 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00015154 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x02888945 | (1<<16)] - while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 } + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}] + while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 } setup_pll $PLL2_BASE_ADDR 400 ; # Switch peripheral to PLL2 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x00808145 | (2<<10) | (9<<16) | (1<<19)] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}] - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00016154 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154 ; # change uart clk parent to pll2 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1]] & 0xfcffffff | 0x01000000] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}] ; # make sure change is effective - while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 } + while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 } setup_pll $PLL3_BASE_ADDR 216 setup_pll $PLL4_BASE_ADDR 455 ; # Set the platform clock dividers - mww [expr $PLATFORM_BASE_ADDR + 0x14] 0x00000124 + mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124 - mww [expr $CCM_BASE_ADDR + 0x10] 0 + mww [expr {$CCM_BASE_ADDR + 0x10}] 0 ; # Switch ARM back to PLL 1. - mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x0 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0 ; # make uart div=6 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1]] & 0xffffffc0 | 0x0a] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}] ; # Restore the default values in the Gate registers - mww [expr $CCM_BASE_ADDR + 0x68] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x6C] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x70] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x74] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x78] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x7C] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x80] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x84] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + $CLKCTL_CCDR] 0x00000 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000 ; # for cko - for ARM div by 8 - mww [expr $CCM_BASE_ADDR + 0x60] [expr 0x000A0000 & 0x00000F0] + mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}] } @@ -183,68 +183,68 @@ proc setup_pll { PLL_ADDR CLK } { set PLL_DP_HFS_MFN 0x24 if {$CLK == 1000} { - set DP_OP [expr (10 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (12 - 1)] + set DP_OP [expr {(10 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {12 - 1}] set DP_MFN 5 } elseif {$CLK == 850} { - set DP_OP [expr (8 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (48 - 1)] + set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {48 - 1}] set DP_MFN 41 } elseif {$CLK == 800} { - set DP_OP [expr (8 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (3 - 1)] + set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {3 - 1}] set DP_MFN 1 } elseif {$CLK == 700} { - set DP_OP [expr (7 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (24 - 1)] + set DP_OP [expr {(7 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {24 - 1}] set DP_MFN 7 } elseif {$CLK == 600} { - set DP_OP [expr (6 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (4 - 1)] + set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {4 - 1}] set DP_MFN 1 } elseif {$CLK == 665} { - set DP_OP [expr (6 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (96 - 1)] + set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {96 - 1}] set DP_MFN 89 } elseif {$CLK == 532} { - set DP_OP [expr (5 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (24 - 1)] + set DP_OP [expr {(5 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {24 - 1}] set DP_MFN 13 } elseif {$CLK == 455} { - set DP_OP [expr (8 << 4) + ((2 - 1) << 0)] - set DP_MFD [expr (48 - 1)] + set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}] + set DP_MFD [expr {48 - 1}] set DP_MFN 71 } elseif {$CLK == 400} { - set DP_OP [expr (8 << 4) + ((2 - 1) << 0)] - set DP_MFD [expr (3 - 1)] + set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}] + set DP_MFD [expr {3 - 1}] set DP_MFN 1 } elseif {$CLK == 216} { - set DP_OP [expr (6 << 4) + ((3 - 1) << 0)] - set DP_MFD [expr (4 - 1)] + set DP_OP [expr {(6 << 4) + ((3 - 1) << 0)}] + set DP_MFD [expr {4 - 1}] set DP_MFN 3 } else { error "Error (setup_dll): clock not found!" } - mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232 - mww [expr $PLL_ADDR + $PLL_DP_CONFIG] 0x2 + mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232 + mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2 - mww [expr $PLL_ADDR + $PLL_DP_OP] $DP_OP - mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_OP + mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP - mww [expr $PLL_ADDR + $PLL_DP_MFD] $DP_MFD - mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_MFD + mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD - mww [expr $PLL_ADDR + $PLL_DP_MFN] $DP_MFN - mww [expr $PLL_ADDR + $PLL_DP_HFS_MFN] $DP_MFN + mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN - mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232 - while {[expr [mrw [expr $PLL_ADDR + $PLL_DP_CTL]] & 0x1] == 0} { sleep 1 } + mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232 + while {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 } } proc CPU_2_BE_32 { L } { - return [expr (($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)] + return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)}] } diff --git a/tcl/board/imx53loco.cfg b/tcl/board/imx53loco.cfg index 91c2601..c4d45f0 100644 --- a/tcl/board/imx53loco.cfg +++ b/tcl/board/imx53loco.cfg @@ -19,7 +19,7 @@ adapter speed 3000 jtag_rclk 1000 $_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 } -#jtag_nsrst_delay 200 +#adapter srst delay 200 #jtag_ntrst_delay 200 $_TARGETNAME configure -event "reset-assert" { @@ -46,7 +46,7 @@ proc loco_init { } { ; # ARM errata ID #468414 set tR [arm mrc 15 0 1 0 1] - arm mcr 15 0 1 0 1 [expr $tR | (1<<5)] ; # enable L1NEON bit + arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}] ; # enable L1NEON bit init_l2cc init_aips @@ -70,7 +70,7 @@ proc init_l2cc { } { set tR [arm mrc 15 0 1 0 1] ; #bic r0, r0, #0x2 ; #mcr 15, 0, r0, c1, c0, 1 - arm mcr 15 0 1 0 1 [expr $tR & ~(1<<2)] + arm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}] ; #/* reconfigure L2 cache aux control reg */ ; #mov r0, #0xC0 /* tag RAM */ @@ -80,7 +80,7 @@ proc init_l2cc { } { ; #orr r0, r0, #(1 << 22) /* disable write allocate */ ; #mcr 15, 1, r0, c9, c0, 2 - arm mcr 15 1 9 0 2 [expr 0xC4 | (1<<24) | (1<<23) | (1<<22)] + arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}] } @@ -94,10 +94,10 @@ proc init_aips { } { set VAL 0x77777777 # dap apsel 1 - mww [expr $AIPS1_BASE_ADDR + 0x0] $VAL - mww [expr $AIPS1_BASE_ADDR + 0x4] $VAL - mww [expr $AIPS2_BASE_ADDR + 0x0] $VAL - mww [expr $AIPS2_BASE_ADDR + 0x4] $VAL + mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL + mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL + mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL + mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL # dap apsel 0 } @@ -105,22 +105,22 @@ proc init_aips { } { proc init_clock { } { global AIPS1_BASE_ADDR global AIPS2_BASE_ADDR - set CCM_BASE_ADDR [expr $AIPS1_BASE_ADDR + 0x000D4000] + set CCM_BASE_ADDR [expr {$AIPS1_BASE_ADDR + 0x000D4000}] set CLKCTL_CCSR 0x0C set CLKCTL_CBCDR 0x14 set CLKCTL_CBCMR 0x18 - set PLL1_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00080000] - set PLL2_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00084000] - set PLL3_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00088000] - set PLL4_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x0008C000] + set PLL1_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00080000}] + set PLL2_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00084000}] + set PLL3_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00088000}] + set PLL4_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x0008C000}] set CLKCTL_CSCMR1 0x1C set CLKCTL_CDHIPR 0x48 - set PLATFORM_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x000A0000] + set PLATFORM_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x000A0000}] set CLKCTL_CSCDR1 0x24 set CLKCTL_CCDR 0x04 ; # Switch ARM to step clock - mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x4 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4 return echo "not returned" @@ -128,52 +128,52 @@ proc init_clock { } { setup_pll $PLL3_BASE_ADDR 400 ; # Switch peripheral to PLL3 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00015154 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x02888945 | (1<<16)] - while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 } + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}] + while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 } setup_pll $PLL2_BASE_ADDR 400 ; # Switch peripheral to PLL2 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x00808145 | (2<<10) | (9<<16) | (1<<19)] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}] - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00016154 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154 ; # change uart clk parent to pll2 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1]] & 0xfcffffff | 0x01000000] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}] ; # make sure change is effective - while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 } + while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 } setup_pll $PLL3_BASE_ADDR 216 setup_pll $PLL4_BASE_ADDR 455 ; # Set the platform clock dividers - mww [expr $PLATFORM_BASE_ADDR + 0x14] 0x00000124 + mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124 - mww [expr $CCM_BASE_ADDR + 0x10] 0 + mww [expr {$CCM_BASE_ADDR + 0x10}] 0 ; # Switch ARM back to PLL 1. - mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x0 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0 ; # make uart div=6 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1]] & 0xffffffc0 | 0x0a] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}] ; # Restore the default values in the Gate registers - mww [expr $CCM_BASE_ADDR + 0x68] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x6C] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x70] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x74] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x78] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x7C] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x80] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x84] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + $CLKCTL_CCDR] 0x00000 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000 ; # for cko - for ARM div by 8 - mww [expr $CCM_BASE_ADDR + 0x60] [expr 0x000A0000 & 0x00000F0] + mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}] } @@ -188,68 +188,68 @@ proc setup_pll { PLL_ADDR CLK } { set PLL_DP_HFS_MFN 0x24 if {$CLK == 1000} { - set DP_OP [expr (10 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (12 - 1)] + set DP_OP [expr {(10 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {12 - 1}] set DP_MFN 5 } elseif {$CLK == 850} { - set DP_OP [expr (8 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (48 - 1)] + set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {48 - 1}] set DP_MFN 41 } elseif {$CLK == 800} { - set DP_OP [expr (8 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (3 - 1)] + set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {3 - 1}] set DP_MFN 1 } elseif {$CLK == 700} { - set DP_OP [expr (7 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (24 - 1)] + set DP_OP [expr {(7 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {24 - 1}] set DP_MFN 7 } elseif {$CLK == 600} { - set DP_OP [expr (6 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (4 - 1)] + set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {4 - 1}] set DP_MFN 1 } elseif {$CLK == 665} { - set DP_OP [expr (6 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (96 - 1)] + set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {96 - 1}] set DP_MFN 89 } elseif {$CLK == 532} { - set DP_OP [expr (5 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (24 - 1)] + set DP_OP [expr {(5 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {24 - 1}] set DP_MFN 13 } elseif {$CLK == 455} { - set DP_OP [expr (8 << 4) + ((2 - 1) << 0)] - set DP_MFD [expr (48 - 1)] + set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}] + set DP_MFD [expr {48 - 1}] set DP_MFN 71 } elseif {$CLK == 400} { - set DP_OP [expr (8 << 4) + ((2 - 1) << 0)] - set DP_MFD [expr (3 - 1)] + set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}] + set DP_MFD [expr {3 - 1}] set DP_MFN 1 } elseif {$CLK == 216} { - set DP_OP [expr (6 << 4) + ((3 - 1) << 0)] - set DP_MFD [expr (4 - 1)] + set DP_OP [expr {(6 << 4) + ((3 - 1) << 0)}] + set DP_MFD [expr {4 - 1}] set DP_MFN 3 } else { error "Error (setup_dll): clock not found!" } - mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232 - mww [expr $PLL_ADDR + $PLL_DP_CONFIG] 0x2 + mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232 + mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2 - mww [expr $PLL_ADDR + $PLL_DP_OP] $DP_OP - mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_OP + mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP - mww [expr $PLL_ADDR + $PLL_DP_MFD] $DP_MFD - mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_MFD + mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD - mww [expr $PLL_ADDR + $PLL_DP_MFN] $DP_MFN - mww [expr $PLL_ADDR + $PLL_DP_HFS_MFN] $DP_MFN + mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN - mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232 - while {[expr [mrw [expr $PLL_ADDR + $PLL_DP_CTL]] & 0x1] == 0} { sleep 1 } + mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232 + while {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 } } proc CPU_2_BE_32 { L } { - return [expr (($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)] + return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)}] } diff --git a/tcl/board/kasli.cfg b/tcl/board/kasli.cfg index 06cc1e6..d492249 100644 --- a/tcl/board/kasli.cfg +++ b/tcl/board/kasli.cfg @@ -3,7 +3,7 @@ ftdi_device_desc "Quad RS232-HS" ftdi_vid_pid 0x0403 0x6011 ftdi_channel 0 ftdi_layout_init 0x0008 0x000b -# ftdi_location 1:8 +# adapter usb location 1:8 reset_config none transport select jtag diff --git a/tcl/board/mcb1700.cfg b/tcl/board/mcb1700.cfg index 01080a0..a5e1902 100644 --- a/tcl/board/mcb1700.cfg +++ b/tcl/board/mcb1700.cfg @@ -55,7 +55,7 @@ $_TARGETNAME configure -event reset-init { # # global MCB1700_CCLK - adapter speed [expr $MCB1700_CCLK / 8] + adapter speed [expr {$MCB1700_CCLK / 8}] # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select # "User Flash Mode" where interrupt vectors are _not_ remapped, diff --git a/tcl/board/mini2440.cfg b/tcl/board/mini2440.cfg index 9dca5a3..3d01b38 100644 --- a/tcl/board/mini2440.cfg +++ b/tcl/board/mini2440.cfg @@ -38,7 +38,7 @@ # it's apt-get install libusb-dev. When I made my config I only included # --enable-jlink and --enable-usbdevs # -# I HAVE NOT Tested this throughly, so there could still be problems. +# I HAVE NOT Tested this thoroughly, so there could still be problems. # But it should get you way ahead of the game from where I started. # If you find problems (and fixes) please post them to # openocd-development@lists.berlios.de and join the developers and diff --git a/tcl/board/nds32_corvettef1.cfg b/tcl/board/nds32_corvettef1.cfg index 1a3782c..cec1723 100644 --- a/tcl/board/nds32_corvettef1.cfg +++ b/tcl/board/nds32_corvettef1.cfg @@ -4,7 +4,7 @@ # ADP-Corvette-F1 R2.0 # http://www.andestech.com/en/products-solutions/andeshape-platforms/corvette-f1-r2/ -adapter_khz 10000 +adapter speed 10000 adapter driver ftdi ftdi_device_desc "Dual RS232-HS" diff --git a/tcl/board/nxp_imx7sabre.cfg b/tcl/board/nxp_imx7sabre.cfg index c595e3a..789fc5b 100644 --- a/tcl/board/nxp_imx7sabre.cfg +++ b/tcl/board/nxp_imx7sabre.cfg @@ -27,7 +27,7 @@ proc imx7_uart_dbgconf { } { } proc check_bits_set_32 { addr mask } { - while { [expr [mrw $addr] & $mask == 0] } { } + while { [expr {[mrw $addr] & $mask} == 0] } { } } proc apply_dcd { } { diff --git a/tcl/board/pico-debug.cfg b/tcl/board/pico-debug.cfg index c2fe7d3..ba59f86 100644 --- a/tcl/board/pico-debug.cfg +++ b/tcl/board/pico-debug.cfg @@ -8,4 +8,3 @@ adapter speed 4000 set CHIPNAME rp2040 source [find target/rp2040-core0.cfg] - diff --git a/tcl/board/sayma_amc.cfg b/tcl/board/sayma_amc.cfg index 009eb78..64c0854 100644 --- a/tcl/board/sayma_amc.cfg +++ b/tcl/board/sayma_amc.cfg @@ -15,7 +15,7 @@ ftdi_device_desc "Quad RS232-HS" ftdi_vid_pid 0x0403 0x6011 ftdi_channel 0 # Use this to distinguish multiple boards by topology -#ftdi_location 5:1 +#adapter usb location 5:1 # sampling on falling edge generally seems to work and accelerates things but # is not fully tested #ftdi_tdo_sample_edge falling diff --git a/tcl/board/snps_hsdk.cfg b/tcl/board/snps_hsdk.cfg index fed7343..a6228f4 100644 --- a/tcl/board/snps_hsdk.cfg +++ b/tcl/board/snps_hsdk.cfg @@ -9,7 +9,7 @@ # source [find interface/ftdi/snps_sdp.cfg] -adapter_khz 10000 +adapter speed 10000 # ARCs supports only JTAG. transport select jtag diff --git a/tcl/board/st_nucleo_8s208rb.cfg b/tcl/board/st_nucleo_8s208rb.cfg new file mode 100644 index 0000000..0d3c0c9 --- /dev/null +++ b/tcl/board/st_nucleo_8s208rb.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is a ST NUCLEO 8S208RB board with a single STM8S208RBT6 chip. +# https://www.st.com/en/evaluation-tools/nucleo-8s208rb.html + +source [find interface/stlink-dap.cfg] + +transport select swim + +# 128 KiB flash and 2 KiB EEPROM +set FLASHEND 0x27fff +set EEPROMEND 0x47ff + +source [find target/stm8s.cfg] + +reset_config srst_only diff --git a/tcl/board/uptech_2410.cfg b/tcl/board/uptech_2410.cfg index 227cf42..0a2c475 100644 --- a/tcl/board/uptech_2410.cfg +++ b/tcl/board/uptech_2410.cfg @@ -1,5 +1,5 @@ # Target Configuration for the Uptech 2410 board. -# This configuration hould also work on smdk2410, but I havn't tested it yet. +# This configuration should also work on smdk2410, but I haven't tested it yet. # Author: xionglingfeng@Gmail.com source [find target/samsung_s3c2410.cfg] |