Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface

- write speed up to 150 kByte/s on STM32F469I-disco (due to
  SWD clock and USB connection), up to 1 MByte/s on Nucleo-F767ZI
  with external STLink-V3 or Nucleo-G474RE with two W25Q256FV in
  dual 4-line mode or STM32H73BI-Disco in octal mode
- tested with STM32L476G-disco (64MBit flash, 3-byte addr),
  STM32F412G-Disco, STM32F469I-Disco, STM32F746G-Disco, and
  STM32L476G-Disco (all 128Mbit flash, 3-byte addr),
  STM32F723E-Disco, STM32F769I-Disco (512Mbit flash, 4-byte addr)
  STM32L4R9I-Disco, STM32L4P5G-Disco (512MBit octo-flash, DTR, 4-byte addr)
  STM32H745I-Disco, STM32H747I-Disco (two 512MBit flash, 4-byte addr)
  STM32H73BI-Disco, STM32H735G-Disco (512MBit octo-flash, DTR, 4-byte addr)
- suitable cfg for Discovery boards included
- limited parsing of SFDP data if flash device not hardcoded
  (tested only in single/quad mode as most devices either don't
  support SFDP at all or have empty(!) SFDP memory)
- 'set' command for auto detection override (e. g. for EEPROMs)
- 'cmd' command for arbitrary SPI commands (reconfiguration, testing etc.)
- makefile for creation of binary loader files
- tcl/board/stm32f469discovery.cfg superseded by stm32f469i-disco.cfg
- tcl/board/stm32f7discovery.cfg removed as name is ambiguous
  (superseded by stm32f746g-disco.cfg vs. stm32f769i-disco.cfg)
- dual 4-line mode tested on Nucleo-F767ZI, Nucleo-H743ZI and Nucleo-H7A3ZI-Q
  with two W25Q256FV, and on Nucleo-L496ZP-P and Nucleo-L4R5ZI
  with two W25Q128FV, sample cfg files included and on STM32H745I-Disco,
  STM32H747I-Disco, STM32H750B-Disco
- read/verify/erase_check uses indirect read mode to work around silicon bug in
  H7, L4+ and MP1 memory mapped mode (last bytes not readable, accessing last
  bytes causes debug interface to hang)
- octospi supported only in single/dual 1-line, 2-line, 4-line
  and single 8-line modes, (not in hyper flash mode)

Requirements:
GPIOs must be initialized appropriately, and SPI flash chip be configured
appropriately (1-line ..., QPI, 4-byte addresses ...). This is board/chip
specific, cf. included cfg files. The driver infers most parameters from
current setting in CR, CCR, ... registers.

Change-Id: I54858fbbe8758c3a5fe58812e93f5f39514704f8
Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-on: http://openocd.zylin.com/4321
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Christopher Head <chead@zaber.com>

21 files changed, 1461 insertions, 1 deletions

diff --git a/tcl/board/b-l475e-iot01a.cfg b/tcl/board/b-l475e-iot01a.cfg
new file mode 100644
index 0000000..be411e4
--- /dev/null
+++ b/tcl/board/b-l475e-iot01a.cfg
@@ -0,0 +1,56 @@
+# This is an B-L475E-IOT01A Discovery kit for IoT node with a single STM32L475VGT6 chip.
+# http://www.st.com/en/evaluation-tools/b-l475e-iot01a.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select hla_swd
+
+# increase working area to 96KB
+set WORKAREASIZE 0x18000
+
+# enable stmqspi
+set QUADSPI 1
+
+source [find target/stm32l4x.cfg]
+
+# QUADSPI initialization
+proc qspi_init { } {
+	global a
+	mmw 0x4002104C 0x000001FF 0				;# RCC_AHB2ENR |= GPIOAEN-GPIOIEN (enable clocks)
+	mmw 0x40021050 0x00000100 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PE11: NCS, PE10: CLK, PE15: BK1_IO3, PE14: BK1_IO2, PE13: BK1_IO1, PE12: BK1_IO0
+
+	# PE15:AF10:V, PE14:AF10:V, PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V
+
+	# Port E: PE15:AF10:V, PE14:AF10:V, PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V
+	mmw 0x48001000 0xAAA00000 0x55500000	;# MODER
+	mmw 0x48001008 0xFFF00000 0x00000000	;# OSPEEDR
+	mmw 0x48001024 0xAAAAAA00 0x55555500	;# AFRH
+
+	mww 0xA0001030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x01500008				;# QUADSPI_CR: PRESCALER=1, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
+	mww 0xA0001004 0x00160100				;# QUADSPI_DCR: FSIZE=0x16, CSHT=0x01, CKMODE=0
+	mmw 0xA0001000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# memory-mapped read mode with 3-byte addresses
+	mww 0xA0001014 0x0D002503				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
+}
+
+$_TARGETNAME configure -event reset-init {
+	mmw 0x40022000 0x00000004 0x00000003	;# 4 WS for 72 MHz HCLK
+	sleep 1
+	mmw 0x40021000 0x00000100 0x00000000	;# HSI on
+	mww 0x4002100C 0x01002432				;# 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI
+	mww 0x40021008 0x00008001				;# always HSI, APB1: /1, APB2: /1
+	mmw 0x40021000 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40021008 0x00000003 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 4000
+
+	qspi_init
+}
diff --git a/tcl/board/stm32f412g-disco.cfg b/tcl/board/stm32f412g-disco.cfg
new file mode 100644
index 0000000..b6bdb64
--- /dev/null
+++ b/tcl/board/stm32f412g-disco.cfg
@@ -0,0 +1,70 @@
+# This is an STM32F412G discovery board with a single STM32F412ZGT6 chip.
+# http://www.st.com/en/evaluation-tools/32f412gdiscovery.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select hla_swd
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+# enable stmqspi
+set QUADSPI 1
+
+source [find target/stm32f4x.cfg]
+
+# QUADSPI initialization
+proc qspi_init { } {
+	global a
+	mmw 0x40023830 0x000000FF 0				;# RCC_AHB1ENR |= GPIOAEN-GPIOHEN (enable clocks)
+	mmw 0x40023838 0x00000002 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PB02: CLK, PG06: BK1_NCS, PF06: BK1_IO3, PF07: BK1_IO2, PF09: BK1_IO1, PF08: BK1_IO0
+
+	# PB02:AF09:V, PF09:AF10:V, PF08:AF10:V, PF07:AF09:V, PF06:AF09:V, PG06:AF10:V
+
+	# Port B: PB02:AF09:V
+	mmw 0x40020400 0x00000020 0x00000010	;# MODER
+	mmw 0x40020408 0x00000030 0x00000000	;# OSPEEDR
+	mmw 0x40020420 0x00000900 0x00000600	;# AFRL
+
+	# Port F: PF09:AF10:V, PF08:AF10:V, PF07:AF09:V, PF06:AF09:V
+	mmw 0x40021400 0x000AA000 0x00055000	;# MODER
+	mmw 0x40021408 0x000FF000 0x00000000	;# OSPEEDR
+	mmw 0x40021420 0x99000000 0x66000000	;# AFRL
+	mmw 0x40021424 0x000000AA 0x00000055	;# AFRH
+
+	# Port G: PG06:AF10:V
+	mmw 0x40021800 0x00002000 0x00001000	;# MODER
+	mmw 0x40021808 0x00003000 0x00000000	;# OSPEEDR
+	mmw 0x40021820 0x0A000000 0x05000000	;# AFRL
+
+	mww 0xA0001030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x03500008				;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
+	mww 0xA0001004 0x00170100				;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0
+	mmw 0xA0001000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# 1-line spi mode
+	mww 0xA0001014 0x000003F5				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
+	sleep 1
+
+	# memory-mapped read mode with 3-byte addresses
+	mww 0xA0001014 0x0D002503				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
+}
+
+$_TARGETNAME configure -event reset-init {
+	mww 0x40023C00 0x00000003				;# 3 WS for 96 MHz HCLK
+	sleep 1
+	mww 0x40023804 0x24001808				;# 96 MHz: HSI, PLLM=8, PLLN=96, PLLP=2
+	mww 0x40023808 0x00001000				;# APB1: /2, APB2: /1
+	mmw 0x40023800 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40023808 0x00000002 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 4000
+
+	qspi_init
+}
diff --git a/tcl/board/stm32f413h-disco.cfg b/tcl/board/stm32f413h-disco.cfg
new file mode 100644
index 0000000..99f2a49
--- /dev/null
+++ b/tcl/board/stm32f413h-disco.cfg
@@ -0,0 +1,83 @@
+# This is an STM32F413H discovery board with a single STM32F413ZHT6 chip.
+# http://www.st.com/en/evaluation-tools/32f413hdiscovery.html
+
+#
+# Untested!!!
+#
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select hla_swd
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+# enable stmqspi
+set QUADSPI 1
+
+source [find target/stm32f4x.cfg]
+
+# QUADSPI initialization
+proc qspi_init { } {
+	global a
+	mmw 0x40023830 0x000000FF 0				;# RCC_AHB1ENR |= GPIOAEN-GPIOHEN (enable clocks)
+	mmw 0x40023838 0x00000002 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PG06: BK1_NCS, PB02: CLK, PD13: BK1_IO3, PE02: BK1_IO2, PF09: BK1_IO1, PF08: BK1_IO0
+
+	# PB02:AF09:V, PD13:AF09:V, PE02:AF09:V, PF09:AF10:V, PF08:AF10:V, PG06:AF10:V
+
+	# Port B: PB02:AF09:V
+	mmw 0x40020400 0x00000020 0x00000010	;# MODER
+	mmw 0x40020408 0x00000030 0x00000000	;# OSPEEDR
+	mmw 0x40020420 0x00000900 0x00000600	;# AFRL
+
+	# Port D: PD13:AF09:V
+	mmw 0x40020C00 0x08000000 0x04000000	;# MODER
+	mmw 0x40020C08 0x0C000000 0x00000000	;# OSPEEDR
+	mmw 0x40020C24 0x00900000 0x00600000	;# AFRH
+
+	# Port E: PE02:AF09:V
+	mmw 0x40021000 0x00000020 0x00000010	;# MODER
+	mmw 0x40021008 0x00000030 0x00000000	;# OSPEEDR
+	mmw 0x40021020 0x00000900 0x00000600	;# AFRL
+
+	# Port F: PF09:AF10:V, PF08:AF10:V
+	mmw 0x40021400 0x000A0000 0x00050000	;# MODER
+	mmw 0x40021408 0x000F0000 0x00000000	;# OSPEEDR
+	mmw 0x40021424 0x000000AA 0x00000055	;# AFRH
+
+	# Port G: PG06:AF10:V
+	mmw 0x40021800 0x00002000 0x00001000	;# MODER
+	mmw 0x40021808 0x00003000 0x00000000	;# OSPEEDR
+	mmw 0x40021820 0x0A000000 0x05000000	;# AFRL
+
+	mww 0xA0001030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x03500008				;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
+	mww 0xA0001004 0x00170100				;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0
+	mmw 0xA0001000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# 1-line spi mode
+	mww 0xA0001014 0x000003F5				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
+	sleep 1
+
+	# memory-mapped read mode with 3-byte addresses
+	mww 0xA0001014 0x0D002503				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
+}
+
+$_TARGETNAME configure -event reset-init {
+	mww 0x40023C00 0x00000003				;# 3 WS for 96 MHz HCLK
+	sleep 1
+	mww 0x40023804 0x24001808				;# 96 MHz: HSI, PLLM=8, PLLN=96, PLLP=2
+	mww 0x40023808 0x00001000				;# APB1: /2, APB2: /1
+	mmw 0x40023800 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40023808 0x00000002 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 4000
+
+	qspi_init
+}
diff --git a/tcl/board/stm32f469i-disco.cfg b/tcl/board/stm32f469i-disco.cfg
new file mode 100644
index 0000000..ab67512
--- /dev/null
+++ b/tcl/board/stm32f469i-disco.cfg
@@ -0,0 +1,65 @@
+# This is an STM32F469I discovery board with a single STM32F469NIH6 chip.
+# http://www.st.com/en/evaluation-tools/32f469idiscovery.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select hla_swd
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+# enable stmqspi
+set QUADSPI 1
+
+source [find target/stm32f4x.cfg]
+
+# QUADSPI initialization
+proc qspi_init { } {
+	global a
+	mmw 0x40023830 0x000007FF 0				;# RCC_AHB1ENR |= GPIOAEN-GPIOKEN (enable clocks)
+	mmw 0x40023838 0x00000002 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PF10: CLK, PB06: BK1_NCS, PF06: BK1_IO3, PF07: BK1_IO2, PF09: BK1_IO1, PF08: BK1_IO0
+
+	# PB06:AF10:V, PF10:AF09:V, PF09:AF10:V, PF08:AF10:V, PF07:AF09:V, PF06:AF09:V
+
+	# Port B: PB06:AF10:V
+	mmw 0x40020400 0x00002000 0x00001000	;# MODER
+	mmw 0x40020408 0x00003000 0x00000000	;# OSPEEDR
+	mmw 0x40020420 0x0A000000 0x05000000	;# AFRL
+
+	# Port F: PF10:AF09:V, PF09:AF10:V, PF08:AF10:V, PF07:AF09:V, PF06:AF09:V
+	mmw 0x40021400 0x002AA000 0x00155000	;# MODER
+	mmw 0x40021408 0x003FF000 0x00000000	;# OSPEEDR
+	mmw 0x40021420 0x99000000 0x66000000	;# AFRL
+	mmw 0x40021424 0x000009AA 0x00000655	;# AFRH
+
+	mww 0xA0001030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x03500008				;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
+	mww 0xA0001004 0x00170100				;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0
+	mmw 0xA0001000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# 1-line spi mode
+	mww 0xA0001014 0x000003F5				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
+	sleep 1
+
+	# memory-mapped read mode with 3-byte addresses
+	mww 0xA0001014 0x0D002503				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
+}
+
+$_TARGETNAME configure -event reset-init {
+	mww 0x40023C00 0x00000005				;# 5 WS for 160 MHz HCLK
+	sleep 1
+	mww 0x40023804 0x24002808				;# 160 MHz: HSI, PLLM=8, PLLN=160, PLLP=2
+	mww 0x40023808 0x00009400				;# APB1: /4, APB2: /2
+	mmw 0x40023800 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40023808 0x00000002 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 4000
+
+	qspi_init
+}
diff --git a/tcl/board/stm32f723e-disco.cfg b/tcl/board/stm32f723e-disco.cfg
new file mode 100644
index 0000000..3c04d86
--- /dev/null
+++ b/tcl/board/stm32f723e-disco.cfg
@@ -0,0 +1,74 @@
+# This is an STM32F723E discovery board with a single STM32F723IEK6 chip.
+# http://www.st.com/en/evaluation-tools/32f723ediscovery.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select hla_swd
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+# enable stmqspi
+set QUADSPI 1
+
+source [find target/stm32f7x.cfg]
+
+# QUADSPI initialization
+proc qspi_init { } {
+	global a
+	mmw 0x40023830 0x000007FF 0				;# RCC_AHB1ENR |= GPIOAEN-GPIOKEN (enable clocks)
+	mmw 0x40023838 0x00000002 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PB02: CLK, PB06: BK1_NCS, PD13: BK1_IO3, PE02: BK1_IO2, PC10: BK1_IO1, PC09: BK1_IO0
+
+	# PB06:AF10:V, PB02:AF09:V, PC10:AF09:V, PC09:AF09:V, PD13:AF09:V, PE02:AF09:V
+
+	# Port B: PB06:AF10:V, PB02:AF09:V
+	mmw 0x40020400 0x00002020 0x00001010	;# MODER
+	mmw 0x40020408 0x00003030 0x00000000	;# OSPEEDR
+	mmw 0x40020420 0x0A000900 0x05000600	;# AFRL
+
+	# Port C: PC10:AF09:V, PC09:AF09:V
+	mmw 0x40020800 0x00280000 0x00140000	;# MODER
+	mmw 0x40020808 0x003C0000 0x00000000	;# OSPEEDR
+	mmw 0x40020824 0x00000990 0x00000660	;# AFRH
+
+	# Port D: PD13:AF09:V
+	mmw 0x40020C00 0x08000000 0x04000000	;# MODER
+	mmw 0x40020C08 0x0C000000 0x00000000	;# OSPEEDR
+	mmw 0x40020C24 0x00900000 0x00600000	;# AFRH
+
+	# Port E: PE02:AF09:V
+	mmw 0x40021000 0x00000020 0x00000010	;# MODER
+	mmw 0x40021008 0x00000030 0x00000000	;# OSPEEDR
+	mmw 0x40021020 0x00000900 0x00000600	;# AFRL
+
+	mww 0xA0001030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x03500008				;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
+	mww 0xA0001004 0x00190100				;# QUADSPI_DCR: FSIZE=0x19, CSHT=0x01, CKMODE=0
+	mmw 0xA0001000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# 1-line spi mode
+	mww 0xA0001014 0x000003F5				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
+	sleep 1
+
+	# memory-mapped read mode with 4-byte addresses
+	mww 0xA0001014 0x0D003513				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=READ
+}
+
+$_TARGETNAME configure -event reset-init {
+	mww 0x40023C00 0x00000006				;# 6 WS for 192 MHz HCLK
+	sleep 1
+	mww 0x40023804 0x24003008				;# 192 MHz: PLLM=8, PLLN=192, PLLP=2
+	mww 0x40023808 0x00009400				;# APB1: /4, APB2: /2
+	mmw 0x40023800 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40023808 0x00000002 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 4000
+
+	qspi_init
+}
diff --git a/tcl/board/stm32f746g-disco.cfg b/tcl/board/stm32f746g-disco.cfg
new file mode 100644
index 0000000..14e89e1
--- /dev/null
+++ b/tcl/board/stm32f746g-disco.cfg
@@ -0,0 +1,69 @@
+# This is an STM32F746G discovery board with a single STM32F746NGH6 chip.
+# http://www.st.com/en/evaluation-tools/32f746gdiscovery.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select hla_swd
+
+# increase working area to 256KB
+set WORKAREASIZE 0x40000
+
+# enable stmqspi
+set QUADSPI 1
+
+source [find target/stm32f7x.cfg]
+
+# QUADSPI initialization
+proc qspi_init { } {
+	global a
+	mmw 0x40023830 0x000007FF 0				;# RCC_AHB1ENR |= GPIOAEN-GPIOKEN (enable clocks)
+	mmw 0x40023838 0x00000002 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PB02: CLK, PB06: BK1_NCS, PD13: BK1_IO3, PE02: BK1_IO2, PD12: BK1_IO1, PD11: BK1_IO0
+
+	# PB06:AF10:V, PB02:AF09:V, PD13:AF09:V, PD12:AF09:V, PD11:AF09:V, PE02:AF09:V
+
+	# Port B: PB06:AF10:V, PB02:AF09:V
+	mmw 0x40020400 0x00002020 0x00001010	;# MODER
+	mmw 0x40020408 0x00003030 0x00000000	;# OSPEEDR
+	mmw 0x40020420 0x0A000900 0x05000600	;# AFRL
+
+	# Port D: PD13:AF09:V, PD12:AF09:V, PD11:AF09:V
+	mmw 0x40020C00 0x0A800000 0x05400000	;# MODER
+	mmw 0x40020C08 0x0FC00000 0x00000000	;# OSPEEDR
+	mmw 0x40020C24 0x00999000 0x00666000	;# AFRH
+
+	# Port E: PE02:AF09:V
+	mmw 0x40021000 0x00000020 0x00000010	;# MODER
+	mmw 0x40021008 0x00000030 0x00000000	;# OSPEEDR
+	mmw 0x40021020 0x00000900 0x00000600	;# AFRL
+
+	mww 0xA0001030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x03500008				;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
+	mww 0xA0001004 0x00170100				;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0
+	mmw 0xA0001000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# 1-line spi mode
+	mww 0xA0001014 0x000003F5				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
+	sleep 1
+
+	# memory-mapped read mode with 3-byte addresses
+	mww 0xA0001014 0x0D002503				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
+}
+
+$_TARGETNAME configure -event reset-init {
+	mww 0x40023C00 0x00000006				;# 6 WS for 192 MHz HCLK
+	sleep 1
+	mww 0x40023804 0x24003008				;# 192 MHz: PLLM=8, PLLN=192, PLLP=2
+	mww 0x40023808 0x00009400				;# APB1: /4, APB2: /2
+	mmw 0x40023800 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40023808 0x00000002 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 4000
+
+	qspi_init
+}
diff --git a/tcl/board/stm32f769i-disco.cfg b/tcl/board/stm32f769i-disco.cfg
new file mode 100644
index 0000000..cc4334b
--- /dev/null
+++ b/tcl/board/stm32f769i-disco.cfg
@@ -0,0 +1,79 @@
+# This is an STM32F769I discovery board with a single STM32F769NIH6 chip.
+# http://www.st.com/en/evaluation-tools/32f769idiscovery.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select hla_swd
+
+# increase working area to 256KB
+set WORKAREASIZE 0x40000
+
+# enable stmqspi
+set QUADSPI 1
+
+source [find target/stm32f7x.cfg]
+
+# QUADSPI initialization
+proc qspi_init { } {
+	global a
+	mmw 0x40023830 0x000007FF 0				;# RCC_AHB1ENR |= GPIOAEN-GPIOKEN (enable clocks)
+	mmw 0x40023838 0x00000002 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PB02: CLK, PB06: BK1_NCS, PD13: BK1_IO3, PE02: BK1_IO2, PC10: BK1_IO1, PC09: BK1_IO0
+
+	# PB06:AF10:V, PB02:AF09:V, PC10:AF09:V, PC09:AF09:V, PD13:AF09:V, PE02:AF09:V
+
+	# Port B: PB06:AF10:V, PB02:AF09:V
+	mmw 0x40020400 0x00002020 0x00001010	;# MODER
+	mmw 0x40020408 0x00003030 0x00000000	;# OSPEEDR
+	mmw 0x40020420 0x0A000900 0x05000600	;# AFRL
+
+	# Port C: PC10:AF09:V, PC09:AF09:V
+	mmw 0x40020800 0x00280000 0x00140000	;# MODER
+	mmw 0x40020808 0x003C0000 0x00000000	;# OSPEEDR
+	mmw 0x40020824 0x00000990 0x00000660	;# AFRH
+
+	# Port D: PD13:AF09:V
+	mmw 0x40020C00 0x08000000 0x04000000	;# MODER
+	mmw 0x40020C08 0x0C000000 0x00000000	;# OSPEEDR
+	mmw 0x40020C24 0x00900000 0x00600000	;# AFRH
+
+	# Port E: PE02:AF09:V
+	mmw 0x40021000 0x00000020 0x00000010	;# MODER
+	mmw 0x40021008 0x00000030 0x00000000	;# OSPEEDR
+	mmw 0x40021020 0x00000900 0x00000600	;# AFRL
+
+	mww 0xA0001030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x03500008				;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
+	mww 0xA0001004 0x00190100				;# QUADSPI_DCR: FSIZE=0x19, CSHT=0x01, CKMODE=0
+	mmw 0xA0001000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# exit qpi mode
+	mww 0xA0001014 0x000033f5				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
+
+	# 1-line memory-mapped read mode with 4-byte addresses
+	mww 0xA0001014 0x0D003513				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=READ
+
+	# 4-line qpi mode
+	mww 0xA0001014 0x00003135				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=EQIO
+
+	# 4-line memory-mapped read mode with 4-byte addresses
+	mww 0xA0001014 0x0F283FEC				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0xA, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=4READ4B
+}
+
+$_TARGETNAME configure -event reset-init {
+	mww 0x40023C00 0x00000006				;# 6 WS for 192 MHz HCLK
+	sleep 1
+	mww 0x40023804 0x24003008				;# 192 MHz: PLLM=8, PLLN=192, PLLP=2
+	mww 0x40023808 0x00009400				;# APB1: /4, APB2: /2
+	mmw 0x40023800 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40023808 0x00000002 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 4000
+
+	qspi_init
+}
diff --git a/tcl/board/stm32h735g-disco.cfg b/tcl/board/stm32h735g-disco.cfg
new file mode 100644
index 0000000..405e470
--- /dev/null
+++ b/tcl/board/stm32h735g-disco.cfg
@@ -0,0 +1,122 @@
+# This is a stm32h735g-dk with a single STM32H735IGK6 chip.
+# https://www.st.com/en/evaluation-tools/stm32h735g-dk.html
+#
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select hla_swd
+
+set CHIPNAME stm32h735igk6
+
+# enable stmqspi
+if {![info exists OCTOSPI1]} {
+	set OCTOSPI1 1
+	set OCTOSPI2 0
+}
+
+source [find target/stm32h7x.cfg]
+
+# OCTOSPI initialization
+# octo: 8-line mode
+proc octospi_init { octo } {
+	global a b
+	mmw 0x58024540 0x000006FF 0				;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks)
+	mmw 0x58024534 0x00284000 0				;# RCC_AHB3ENR |= IOMNGREN, OSPI2EN, OSPI1EN (enable clocks)
+	sleep 1									;# Wait for clock startup
+
+	mww 0x5200B404 0x03010111				;# OCTOSPIM_P1CR: assign Port 1 to OCTOSPI1
+	mww 0x5200B408 0x00000000				;# OCTOSPIM_P2CR: disable Port 2
+
+	# PG06: OCSPI1_NCS, PF10: OCSPI1_CLK, PB02: OCSPI1_DQS, PD07: OCSPI1_IO7, PG09: OCSPI1_IO6, PD05: OCSPI1_IO5,
+	# PD04: OCSPI1_IO4, PD13: OCSPI1_IO3, PE02: OCSPI1_IO2, PD12: OCSPI1_IO1, PD11: OCSPI1_IO0
+
+	# PB02:AF10:V, PD13:AF09:V, PD12:AF09:V, PD11:AF09:V, PD07:AF10:V, PD05:AF10:V
+	# PD04:AF10:V, PE02:AF09:V, PF10:AF09:V, PG09:AF09:V, PG06:AF10:V
+	# Port B: PB02:AF10:V
+	mmw 0x58020400 0x00000020 0x00000010	;# MODER
+	mmw 0x58020408 0x00000030 0x00000000	;# OSPEEDR
+	mmw 0x5802040C 0x00000000 0x00000030	;# PUPDR
+	mmw 0x58020420 0x00000A00 0x00000500	;# AFRL
+	# Port D: PD13:AF09:V, PD12:AF09:V, PD11:AF09:V, PD07:AF10:V, PD05:AF10:V, PD04:AF10:V
+	mmw 0x58020C00 0x0A808A00 0x05404500	;# MODER
+	mmw 0x58020C08 0x0FC0CF00 0x00000000	;# OSPEEDR
+	mmw 0x58020C0C 0x00000000 0x0FC0CF00	;# PUPDR
+	mmw 0x58020C20 0xA0AA0000 0x50550000	;# AFRL
+	mmw 0x58020C24 0x00999000 0x00666000	;# AFRH
+	# Port E: PE02:AF09:V
+	mmw 0x58021000 0x00000020 0x00000010	;# MODER
+	mmw 0x58021008 0x00000030 0x00000000	;# OSPEEDR
+	mmw 0x5802100C 0x00000000 0x00000030	;# PUPDR
+	mmw 0x58021020 0x00000900 0x00000600	;# AFRL
+	# Port F: PF10:AF09:V
+	mmw 0x58021400 0x00200000 0x00100000	;# MODER
+	mmw 0x58021408 0x00300000 0x00000000	;# OSPEEDR
+	mmw 0x5802140C 0x00000000 0x00300000	;# PUPDR
+	mmw 0x58021424 0x00000900 0x00000600	;# AFRH
+	# Port G: PG09:AF09:V, PG06:AF10:V
+	mmw 0x58021800 0x00082000 0x00041000	;# MODER
+	mmw 0x58021808 0x000C3000 0x00000000	;# OSPEEDR
+	mmw 0x5802180C 0x00000000 0x000C3000	;# PUPDR
+	mmw 0x58021820 0x0A000000 0x05000000	;# AFRL
+	mmw 0x58021824 0x00000090 0x00000060	;# AFRH
+
+	# OCTOSPI1: memory-mapped 1-line read mode with 4-byte addresses
+	mww 0x52005130 0x00001000				;# OCTOSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0x52005000 0x3040000B				;# OCTOSPI_CR: FMODE=0x1, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=0
+	mww 0x52005008 0x01190100				;# OCTOSPI_DCR1: MTYP=0x1, FSIZE=0x19, CSHT=0x01, CKMODE=0, DLYBYP=0
+	mww 0x5200500C 0x00000005				;# OCTOSPI_DCR2: PRESCALER=5
+
+	mww 0x52005108 0x00000000				;# OCTOSPI_TCR: SSHIFT=0, DHQC=0, DCYC=0x0
+	mww 0x52005100 0x01003101				;# OCTOSPI_CCR: DMODE=0x1, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x1, ISIZE=0x0, IMODE=0x1
+	mww 0x52005110 0x00000013				;# OCTOSPI_IR: INSTR=READ4B
+
+	flash probe $a							;# load configuration from CR, TCR, CCR, IR register values
+
+	if { $octo == 1 } {
+		stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00			;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
+		stmqspi cmd $a 0 0x06								;# Write Enable
+		stmqspi cmd $a 1 0x05								;# Read Status Register
+		stmqspi cmd $a 0 0x72 0x00 0x00 0x00 0x00 0x02		;# Write Conf. Reg. 2, addr 0x00000000: DTR OPI enable
+
+		# OCTOSPI1: memory-mapped 8-line read mode with 4-byte addresses
+		mww 0x52005000 0x3040000B				;# OCTOSPI_CR: FMODE=0x3, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=1, EN=1
+		mww 0x52005108 0x10000006				;# OCTOSPI_TCR: SSHIFT=0, DHQC=1, DCYC=0x6
+		mww 0x52005100 0x2C003C1C				;# OCTOSPI_CCR: DTR, DMODE=0x4, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x4, ISIZE=0x1, IMODE=0x4
+		mww 0x52005110 0x0000EE11				;# OCTOSPI_IR: INSTR=OCTA DTR Read
+
+		flash probe $a							;# reload configuration from CR, TCR, CCR, IR register values
+
+		stmqspi cmd $a 0 0x06								;# Write Enable
+		stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00			;# Read Status Register (note dummy address in 8-line mode)
+		stmqspi cmd $a 0 0x04								;# Write Disable
+		stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00			;# Read Status Register (note dummy address in 8-line mode)
+		stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00			;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
+	}
+}
+
+$_CHIPNAME.cpu0 configure -event reset-init {
+	global OCTOSPI1
+	global OCTOSPI2
+
+	mmw 0x52002000 0x00000004 0x0000000B	;# FLASH_ACR: 4 WS for 192 MHZ HCLK
+
+	mmw 0x58024400 0x00000001 0x00000018	;# RCC_CR: HSIDIV=1, HSI on
+	mmw 0x58024410 0x10000000 0xEE000007	;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock
+	mww 0x58024418 0x00000040				;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1
+	mww 0x5802441C 0x00000440				;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2
+	mww 0x58024420 0x00000040				;# RCC_D3CFGR: D3PPRE=2
+	mww 0x58024428 0x00000040				;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI
+	mmw 0x5802442C 0x0001000C 0x00000002	;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide
+	mww 0x58024430 0x01070217				;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24
+	mmw 0x58024400 0x01000000 0				;# RCC_CR: PLL1ON=1
+	sleep 1
+	mmw 0x58024410 0x00000003 0				;# RCC_CFGR: PLL1 as system clock
+	sleep 1
+
+	adapter speed 24000
+
+	if { $OCTOSPI1 } {
+		octospi_init 1
+	}
+}
diff --git a/tcl/board/stm32h745i-disco.cfg b/tcl/board/stm32h745i-disco.cfg
new file mode 100644
index 0000000..5adcfea
--- /dev/null
+++ b/tcl/board/stm32h745i-disco.cfg
@@ -0,0 +1,45 @@
+# This is a stm32h745i-disco with a single STM32H745XIH6 chip.
+# www.st.com/en/product/stm32h745i-disco.html
+#
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select hla_swd
+
+set CHIPNAME stm32h745xih6
+
+# enable stmqspi
+if {![info exists QUADSPI]} {
+	set QUADSPI 1
+}
+
+source [find target/stm32h7x_dual_bank.cfg]
+
+source [find board/stm32h7x_dual_qspi.cfg]
+
+$_CHIPNAME.cpu0 configure -event reset-init {
+	global QUADSPI
+
+	mmw 0x52002000 0x00000004 0x0000000B	;# FLASH_ACR: 4 WS for 192 MHZ HCLK
+
+	mmw 0x58024400 0x00000001 0x00000018	;# RCC_CR: HSIDIV=1, HSI on
+	mmw 0x58024410 0x10000000 0xEE000007	;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock
+	mww 0x58024418 0x00000040				;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1
+	mww 0x5802441C 0x00000440				;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2
+	mww 0x58024420 0x00000040				;# RCC_D3CFGR: D3PPRE=2
+	mww 0x58024428 0x00000040				;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI
+	mmw 0x5802442C 0x0001000C 0x00000002	;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide
+	mww 0x58024430 0x01070217				;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24
+	mmw 0x58024400 0x01000000 0				;# RCC_CR: PLL1ON=1
+	sleep 1
+	mmw 0x58024410 0x00000003 0				;# RCC_CFGR: PLL1 as system clock
+	sleep 1
+
+	adapter speed 24000
+
+	if { $QUADSPI } {
+		qspi_init 1
+	}
+}
+
diff --git a/tcl/board/stm32h747i-disco.cfg b/tcl/board/stm32h747i-disco.cfg
new file mode 100644
index 0000000..22fd74a
--- /dev/null
+++ b/tcl/board/stm32h747i-disco.cfg
@@ -0,0 +1,136 @@
+# This is a stm32h747i-disco with a single STM32H747XIH6 chip.
+# www.st.com/en/product/stm32h747i-disco.html
+#
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select hla_swd
+
+set CHIPNAME stm32h747xih6
+
+# enable stmqspi
+if {![info exists QUADSPI]} {
+	set QUADSPI 1
+}
+
+source [find target/stm32h7x_dual_bank.cfg]
+
+# QUADSPI initialization
+# qpi: 4-line mode
+proc qspi_init { qpi } {
+	global a
+	mmw 0x580244E0 0x000007FF 0				;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks)
+	mmw 0x580244D4 0x00004000 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PG06: BK1_NCS, PB02: CLK, PF06: BK1_IO3, PF07: BK1_IO2, PF09: BK1_IO1, PD11: BK1_IO0,
+	# PG14: BK2_IO3, PG09: BK2_IO2, PH03: BK2_IO1, PH02: BK2_IO0
+
+	# PB02:AF09:V, PD11:AF09:V, PF09:AF10:V, PF07:AF09:V, PF06:AF09:V, PG14:AF09:H
+	# PG09:AF09:V, PG06:AF10:H, PH03:AF09:V, PH02:AF09:V
+
+	# Port B: PB02:AF09:V
+	mmw 0x58020400 0x00000020 0x00000010	;# MODER
+	mmw 0x58020408 0x00000030 0x00000000	;# OSPEEDR
+	mmw 0x58020420 0x00000900 0x00000600	;# AFRL
+	# Port D: PD11:AF09:V
+	mmw 0x58020C00 0x00800000 0x00400000	;# MODER
+	mmw 0x58020C08 0x00C00000 0x00000000	;# OSPEEDR
+	mmw 0x58020C24 0x00009000 0x00006000	;# AFRH
+	# Port F: PF09:AF10:V, PF07:AF09:V, PF06:AF09:V
+	mmw 0x58021400 0x0008A000 0x00045000	;# MODER
+	mmw 0x58021408 0x000CF000 0x00000000	;# OSPEEDR
+	mmw 0x58021420 0x99000000 0x66000000	;# AFRL
+	mmw 0x58021424 0x000000A0 0x00000050	;# AFRH
+	# Port G: PG14:AF09:H, PG09:AF09:V, PG06:AF10:H
+	mmw 0x58021800 0x20082000 0x10041000	;# MODER
+	mmw 0x58021808 0x200C2000 0x10001000	;# OSPEEDR
+	mmw 0x58021820 0x0A000000 0x05000000	;# AFRL
+	mmw 0x58021824 0x09000090 0x06000060	;# AFRH
+	# Port H: PH03:AF09:V, PH02:AF09:V
+	mmw 0x58021C00 0x000000A0 0x00000050	;# MODER
+	mmw 0x58021C08 0x000000F0 0x00000000	;# OSPEEDR
+	mmw 0x58021C20 0x00009900 0x00006600	;# AFRL
+
+	# correct FSIZE is 0x1A, however, this causes trouble when
+	# reading the last bytes at end of bank in *memory mapped* mode
+
+	# for dual flash mode 2 * mt25ql512
+	mww 0x52005000 0x05500058				;# QUADSPI_CR: PRESCALER=5, APMS=1, FTHRES=0, FSEL=0, DFM=1, SSHIFT=1, TCEN=1
+	mww 0x52005004 0x001A0200				;# QUADSPI_DCR: FSIZE=0x1A, CSHT=0x02, CKMODE=0
+
+	mww 0x52005030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0x52005014 0x0D002503				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1
+	mmw 0x52005000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# Exit QPI mode
+	mmw 0x52005000 0x00000002 0				;# QUADSPI_CR: ABORT=1
+	mww 0x52005014 0x000003F5				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=Exit QPI
+	sleep 1
+
+	if { $qpi == 1 } {
+		# Write Enable
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x00000106			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable
+		sleep 1
+
+		# Configure dummy clocks via volatile configuration register
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005010 0x00000001			;# QUADSPI_DLR: 2 data bytes
+		mww 0x52005014 0x01000181			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Volatile Conf. Reg.
+		mwh 0x52005020 0xABAB				;# QUADSPI_DR: 0xAB 0xAB for 10 dummy clocks
+		sleep 1
+
+		# Write Enable
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x00000106			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable
+		sleep 1
+
+		# Enable QPI mode via enhanced volatile configuration register
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005010 0x00000001			;# QUADSPI_DLR: 2 data bytes
+		mww 0x52005014 0x01000161			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enhanced Conf. Reg.
+		mwh 0x52005020 0x3F3F				;# QUADSPI_DR: 0x3F 0x3F to enable QPI and DPI mode
+		sleep 1
+
+		# Enter QPI mode
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x00000135			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Enter QPI
+		sleep 1
+
+		# memory-mapped fast read mode with 4-byte addresses and 10 dummy cycles (for read only)
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x0F283FEC			;# QUADSPI_CCR: FMODE=0x3, DMODE=0x3, DCYC=0xA, ADSIZE=0x3, ADMODE=0x3, IMODE=0x3, INSTR=Fast READ
+	} else {
+		# memory-mapped read mode with 4-byte addresses
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x0D003513			;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=READ
+	}
+}
+
+$_CHIPNAME.cpu0 configure -event reset-init {
+	global QUADSPI
+
+	mmw 0x52002000 0x00000004 0x0000000B	;# FLASH_ACR: 4 WS for 192 MHZ HCLK
+
+	mmw 0x58024400 0x00000001 0x00000018	;# RCC_CR: HSIDIV=1, HSI on
+	mmw 0x58024410 0x10000000 0xEE000007	;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock
+	mww 0x58024418 0x00000040				;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1
+	mww 0x5802441C 0x00000440				;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2
+	mww 0x58024420 0x00000040				;# RCC_D3CFGR: D3PPRE=2
+	mww 0x58024428 0x00000040				;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI
+	mmw 0x5802442C 0x0001000C 0x00000002	;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide
+	mww 0x58024430 0x01070217				;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24
+	mmw 0x58024400 0x01000000 0				;# RCC_CR: PLL1ON=1
+	sleep 1
+	mmw 0x58024410 0x00000003 0				;# RCC_CFGR: PLL1 as system clock
+	sleep 1
+
+	adapter speed 24000
+
+	if { $QUADSPI } {
+		qspi_init 1
+	}
+}
+
diff --git a/tcl/board/stm32h750b-disco.cfg b/tcl/board/stm32h750b-disco.cfg
new file mode 100644
index 0000000..e606203
--- /dev/null
+++ b/tcl/board/stm32h750b-disco.cfg
@@ -0,0 +1,45 @@
+# This is a stm32h750b-dk with a single STM32H750XBH6 chip.
+# www.st.com/en/product/stm32h750b-dk.html
+#
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select hla_swd
+
+set CHIPNAME stm32h750xbh6
+
+# enable stmqspi
+if {![info exists QUADSPI]} {
+	set QUADSPI 1
+}
+
+source [find target/stm32h7x.cfg]
+
+source [find board/stm32h7x_dual_qspi.cfg]
+
+$_CHIPNAME.cpu0 configure -event reset-init {
+	global QUADSPI
+
+	mmw 0x52002000 0x00000004 0x0000000B	;# FLASH_ACR: 4 WS for 192 MHZ HCLK
+
+	mmw 0x58024400 0x00000001 0x00000018	;# RCC_CR: HSIDIV=1, HSI on
+	mmw 0x58024410 0x10000000 0xEE000007	;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock
+	mww 0x58024418 0x00000040				;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1
+	mww 0x5802441C 0x00000440				;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2
+	mww 0x58024420 0x00000040				;# RCC_D3CFGR: D3PPRE=2
+	mww 0x58024428 0x00000040				;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI
+	mmw 0x5802442C 0x0001000C 0x00000002	;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide
+	mww 0x58024430 0x01070217				;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24
+	mmw 0x58024400 0x01000000 0				;# RCC_CR: PLL1ON=1
+	sleep 1
+	mmw 0x58024410 0x00000003 0				;# RCC_CFGR: PLL1 as system clock
+	sleep 1
+
+	adapter speed 24000
+
+	if { $QUADSPI } {
+		qspi_init 1
+	}
+}
+
diff --git a/tcl/board/stm32h7b3i-disco.cfg b/tcl/board/stm32h7b3i-disco.cfg
new file mode 100644
index 0000000..e5512ea
--- /dev/null
+++ b/tcl/board/stm32h7b3i-disco.cfg
@@ -0,0 +1,128 @@
+# This is a stm32h7b3i-dk with a single STM32H7B3LIH6Q chip.
+# https://www.st.com/en/evaluation-tools/stm32h7b3i-dk.html
+#
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select hla_swd
+
+set CHIPNAME stm32h7b3lih6q
+
+# enable stmqspi
+if {![info exists OCTOSPI1]} {
+	set OCTOSPI1 1
+	set OCTOSPI2 0
+}
+
+source [find target/stm32h7x_dual_bank.cfg]
+
+# OCTOSPI initialization
+# octo: 8-line mode
+proc octospi_init { octo } {
+	global a b
+	mmw 0x58024540 0x000007FF 0				;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks)
+	mmw 0x58024534 0x00284000 0				;# RCC_AHB3ENR |= IOMNGREN, OSPI2EN, OSPI1EN (enable clocks)
+	sleep 1									;# Wait for clock startup
+
+	mww 0x5200B404 0x03010111				;# OCTOSPIM_P1CR: assign Port 1 to OCTOSPI1
+	mww 0x5200B408 0x00000000				;# OCTOSPIM_P2CR: disable Port 2
+
+	# PG06: OCSPI1_NCS, PB02: OCSPI1_CLK, PC05: OCSPI1_DQS, PD07: OCSPI1_IO7, PG09: OCSPI1_IO6, PH03: OCSPI1_IO5,
+	# PC01: OCSPI1_IO4, PF06: OCSPI1_IO3, PF07: OCSPI1_IO2, PF09: OCSPI1_IO1, PD11: OCSPI1_IO0
+
+	# PB02:AF09:V, PC05:AF10:V, PC01:AF10:V, PD11:AF09:V, PD07:AF10:V, PF09:AF10:V
+	# PF07:AF10:V, PF06:AF10:V, PG09:AF09:V, PG06:AF10:V, PH03:AF09:V
+	# Port B: PB02:AF09:V
+	mmw 0x58020400 0x00000020 0x00000010	;# MODER
+	mmw 0x58020408 0x00000030 0x00000000	;# OSPEEDR
+	mmw 0x5802040C 0x00000000 0x00000030	;# PUPDR
+	mmw 0x58020420 0x00000900 0x00000600	;# AFRL
+	# Port C: PC05:AF10:V, PC01:AF10:V
+	mmw 0x58020800 0x00000808 0x00000404	;# MODER
+	mmw 0x58020808 0x00000C0C 0x00000000	;# OSPEEDR
+	mmw 0x5802080C 0x00000000 0x00000C0C	;# PUPDR
+	mmw 0x58020820 0x00A000A0 0x00500050	;# AFRL
+	# Port D: PD11:AF09:V, PD07:AF10:V
+	mmw 0x58020C00 0x00808000 0x00404000	;# MODER
+	mmw 0x58020C08 0x00C0C000 0x00000000	;# OSPEEDR
+	mmw 0x58020C0C 0x00000000 0x00C0C000	;# PUPDR
+	mmw 0x58020C20 0xA0000000 0x50000000	;# AFRL
+	mmw 0x58020C24 0x00009000 0x00006000	;# AFRH
+	# Port F: PF09:AF10:V, PF07:AF10:V, PF06:AF10:V
+	mmw 0x58021400 0x0008A000 0x00045000	;# MODER
+	mmw 0x58021408 0x000CF000 0x00000000	;# OSPEEDR
+	mmw 0x5802140C 0x00000000 0x000CF000	;# PUPDR
+	mmw 0x58021420 0xAA000000 0x55000000	;# AFRL
+	mmw 0x58021424 0x000000A0 0x00000050	;# AFRH
+	# Port G: PG09:AF09:V, PG06:AF10:V
+	mmw 0x58021800 0x00082000 0x00041000	;# MODER
+	mmw 0x58021808 0x000C3000 0x00000000	;# OSPEEDR
+	mmw 0x5802180C 0x00000000 0x000C3000	;# PUPDR
+	mmw 0x58021820 0x0A000000 0x05000000	;# AFRL
+	mmw 0x58021824 0x00000090 0x00000060	;# AFRH
+	# Port H: PH03:AF09:V
+	mmw 0x58021C00 0x00000080 0x00000040	;# MODER
+	mmw 0x58021C08 0x000000C0 0x00000000	;# OSPEEDR
+	mmw 0x58021C0C 0x00000000 0x000000C0	;# PUPDR
+	mmw 0x58021C20 0x00009000 0x00006000	;# AFRL
+
+	# OCTOSPI1: memory-mapped 1-line read mode with 4-byte addresses
+	mww 0x52005130 0x00001000				;# OCTOSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0x52005000 0x3040000B				;# OCTOSPI_CR: FMODE=0x1, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=0
+	mww 0x52005008 0x01190100				;# OCTOSPI_DCR1: MTYP=0x1, FSIZE=0x19, CSHT=0x01, CKMODE=0, DLYBYP=0
+	mww 0x5200500C 0x00000005				;# OCTOSPI_DCR2: PRESCALER=5
+
+	mww 0x52005108 0x00000000				;# OCTOSPI_TCR: SSHIFT=0, DHQC=0, DCYC=0x0
+	mww 0x52005100 0x01003101				;# OCTOSPI_CCR: DMODE=0x1, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x1, ISIZE=0x0, IMODE=0x1
+	mww 0x52005110 0x00000013				;# OCTOSPI_IR: INSTR=READ4B
+
+	flash probe $a							;# load configuration from CR, TCR, CCR, IR register values
+
+	if { $octo == 1 } {
+		stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00			;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
+		stmqspi cmd $a 0 0x06								;# Write Enable
+		stmqspi cmd $a 1 0x05								;# Read Status Register
+		stmqspi cmd $a 0 0x72 0x00 0x00 0x00 0x00 0x02		;# Write Conf. Reg. 2, addr 0x00000000: DTR OPI enable
+
+		# OCTOSPI1: memory-mapped 8-line read mode with 4-byte addresses
+		mww 0x52005000 0x3040000B				;# OCTOSPI_CR: FMODE=0x3, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=1, EN=1
+		mww 0x52005108 0x10000006				;# OCTOSPI_TCR: SSHIFT=0, DHQC=1, DCYC=0x6
+		mww 0x52005100 0x2C003C1C				;# OCTOSPI_CCR: DTR, DMODE=0x4, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x4, ISIZE=0x1, IMODE=0x4
+		mww 0x52005110 0x0000EE11				;# OCTOSPI_IR: INSTR=OCTA DTR Read
+
+		flash probe $a							;# reload configuration from CR, TCR, CCR, IR register values
+
+		stmqspi cmd $a 0 0x06								;# Write Enable
+		stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00			;# Read Status Register (note dummy address in 8-line mode)
+		stmqspi cmd $a 0 0x04								;# Write Disable
+		stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00			;# Read Status Register (note dummy address in 8-line mode)
+		stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00			;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
+	}
+}
+
+$_CHIPNAME.cpu0 configure -event reset-init {
+	global OCTOSPI1
+	global OCTOSPI2
+
+	mmw 0x52002000 0x00000004 0x0000000B	;# FLASH_ACR: 4 WS for 192 MHZ HCLK
+
+	mmw 0x58024400 0x00000001 0x00000018	;# RCC_CR: HSIDIV=1, HSI on
+	mmw 0x58024410 0x10000000 0xEE000007	;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock
+	mww 0x58024418 0x00000040				;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1
+	mww 0x5802441C 0x00000440				;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2
+	mww 0x58024420 0x00000040				;# RCC_D3CFGR: D3PPRE=2
+	mww 0x58024428 0x00000040				;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI
+	mmw 0x5802442C 0x0001000C 0x00000002	;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide
+	mww 0x58024430 0x01070217				;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24
+	mmw 0x58024400 0x01000000 0				;# RCC_CR: PLL1ON=1
+	sleep 1
+	mmw 0x58024410 0x00000003 0				;# RCC_CFGR: PLL1 as system clock
+	sleep 1
+
+	adapter speed 24000
+
+	if { $OCTOSPI1 } {
+		octospi_init 1
+	}
+}
diff --git a/tcl/board/stm32h7x_dual_qspi.cfg b/tcl/board/stm32h7x_dual_qspi.cfg
new file mode 100644
index 0000000..bdff9c1
--- /dev/null
+++ b/tcl/board/stm32h7x_dual_qspi.cfg
@@ -0,0 +1,90 @@
+# stm32h754i-disco and stm32h750b-dk dual quad qspi.
+
+# QUADSPI initialization
+# qpi: 4-line mode
+proc qspi_init { qpi } {
+	global a
+	mmw 0x580244E0 0x000007FF 0				;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks)
+	mmw 0x580244D4 0x00004000 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PG06: BK1_NCS, PF10: CLK, PF06: BK1_IO3, PF07: BK1_IO2, PF09: BK1_IO1, PD11: BK1_IO0,
+	# PG14: BK2_IO3, PG09: BK2_IO2, PH03: BK2_IO1, PH02: BK2_IO0
+
+	# PD11:AF09:V, PF10:AF09:V, PF09:AF10:V, PF07:AF09:V, PF06:AF09:V, PG14:AF09:H
+	# PG09:AF09:V, PG06:AF10:H, PH03:AF09:V, PH02:AF09:V
+
+	# Port D: PD11:AF09:V
+	mmw 0x58020C00 0x00800000 0x00400000	;# MODER
+	mmw 0x58020C08 0x00C00000 0x00000000	;# OSPEEDR
+	mmw 0x58020C24 0x00009000 0x00006000	;# AFRH
+	# Port F: PF10:AF09:V, PF09:AF10:V, PF07:AF09:V, PF06:AF09:V
+	mmw 0x58021400 0x0028A000 0x00145000	;# MODER
+	mmw 0x58021408 0x003CF000 0x00000000	;# OSPEEDR
+	mmw 0x58021420 0x99000000 0x66000000	;# AFRL
+	mmw 0x58021424 0x000009A0 0x00000650	;# AFRH
+	# Port G: PG14:AF09:H, PG09:AF09:V, PG06:AF10:H
+	mmw 0x58021800 0x20082000 0x10041000	;# MODER
+	mmw 0x58021808 0x200C2000 0x10001000	;# OSPEEDR
+	mmw 0x58021820 0x0A000000 0x05000000	;# AFRL
+	mmw 0x58021824 0x09000090 0x06000060	;# AFRH
+	# Port H: PH03:AF09:V, PH02:AF09:V
+	mmw 0x58021C00 0x000000A0 0x00000050	;# MODER
+	mmw 0x58021C08 0x000000F0 0x00000000	;# OSPEEDR
+	mmw 0x58021C20 0x00009900 0x00006600	;# AFRL
+
+	# correct FSIZE is 0x1A, however, this causes trouble when
+	# reading the last bytes at end of bank in *memory mapped* mode
+
+	# for dual flash mode 2 * mt25ql512
+	mww 0x52005000 0x05500058				;# QUADSPI_CR: PRESCALER=5, APMS=1, FTHRES=0, FSEL=0, DFM=1, SSHIFT=1, TCEN=1
+	mww 0x52005004 0x001A0200				;# QUADSPI_DCR: FSIZE=0x1A, CSHT=0x02, CKMODE=0
+
+	mww 0x52005030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0x52005014 0x0D002503				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1
+	mmw 0x52005000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# Exit QPI mode
+	mmw 0x52005000 0x00000002 0				;# QUADSPI_CR: ABORT=1
+	mww 0x52005014 0x000003F5				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=Exit QPI
+	sleep 1
+
+	if { $qpi == 1 } {
+		# Write Enable
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x00000106			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable
+		sleep 1
+
+		# Configure dummy clocks via volatile configuration register
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005010 0x00000001			;# QUADSPI_DLR: 2 data bytes
+		mww 0x52005014 0x01000181			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Volatile Conf. Reg.
+		mwh 0x52005020 0xABAB				;# QUADSPI_DR: 0xAB 0xAB for 10 dummy clocks
+		sleep 1
+
+		# Write Enable
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x00000106			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable
+		sleep 1
+
+		# Enable QPI mode via enhanced volatile configuration register
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005010 0x00000001			;# QUADSPI_DLR: 2 data bytes
+		mww 0x52005014 0x01000161			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enhanced Conf. Reg.
+		mwh 0x52005020 0x3F3F				;# QUADSPI_DR: 0x3F 0x3F to enable QPI and DPI mode
+		sleep 1
+
+		# Enter QPI mode
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x00000135			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Enter QPI
+		sleep 1
+
+		# memory-mapped fast read mode with 4-byte addresses and 10 dummy cycles (for read only)
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x0F283FEC			;# QUADSPI_CCR: FMODE=0x3, DMODE=0x3, DCYC=0xA, ADSIZE=0x3, ADMODE=0x3, IMODE=0x3, INSTR=Fast READ
+	} else {
+		# memory-mapped read mode with 4-byte addresses
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x0D003513			;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=READ
+	}
+}
diff --git a/tcl/board/stm32l476g-disco.cfg b/tcl/board/stm32l476g-disco.cfg
new file mode 100644
index 0000000..dab2fe1
--- /dev/null
+++ b/tcl/board/stm32l476g-disco.cfg
@@ -0,0 +1,56 @@
+# This is an STM32L476G discovery board with a single STM32L476VGT6 chip.
+# http://www.st.com/en/evaluation-tools/32l476gdiscovery.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select hla_swd
+
+# increase working area to 96KB
+set WORKAREASIZE 0x18000
+
+# enable stmqspi
+set QUADSPI 1
+
+source [find target/stm32l4x.cfg]
+
+# QUADSPI initialization
+proc qspi_init { } {
+	global a
+	mmw 0x4002104C 0x000001FF 0				;# RCC_AHB2ENR |= GPIOAEN-GPIOIEN (enable clocks)
+	mmw 0x40021050 0x00000100 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PE11: NCS, PE10: CLK, PE15: BK1_IO3, PE14: BK1_IO2, PE13: BK1_IO1, PE12: BK1_IO0
+
+	# PE15:AF10:V, PE14:AF10:V, PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V
+
+	# Port E: PE15:AF10:V, PE14:AF10:V, PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V
+	mmw 0x48001000 0xAAA00000 0x55500000    ;# MODER
+	mmw 0x48001008 0xFFF00000 0x00000000    ;# OSPEEDR
+	mmw 0x48001024 0xAAAAAA00 0x55555500    ;# AFRH
+
+	mww 0xA0001030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x01500008				;# QUADSPI_CR: PRESCALER=1, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
+	mww 0xA0001004 0x00170100				;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0
+	mmw 0xA0001000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# memory-mapped read mode with 3-byte addresses
+	mww 0xA0001014 0x0D002503				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
+}
+
+$_TARGETNAME configure -event reset-init {
+	mmw 0x40022000 0x00000004 0x00000003	;# 4 WS for 72 MHz HCLK
+	sleep 1
+	mmw 0x40021000 0x00000100 0x00000000	;# HSI on
+	mww 0x4002100C 0x01002432				;# 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI
+	mww 0x40021008 0x00008001				;# always HSI, APB1: /1, APB2: /1
+	mmw 0x40021000 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40021008 0x00000003 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 4000
+
+	qspi_init
+}
diff --git a/tcl/board/stm32l496g-disco.cfg b/tcl/board/stm32l496g-disco.cfg
new file mode 100644
index 0000000..a93b07c
--- /dev/null
+++ b/tcl/board/stm32l496g-disco.cfg
@@ -0,0 +1,66 @@
+# This is an STM32L496G discovery board with a single STM32L496AGI6 chip.
+# http://www.st.com/en/evaluation-tools/32l496gdiscovery.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select hla_swd
+
+# increase working area to 96KB
+set WORKAREASIZE 0x18000
+
+# enable stmqspi
+set QUADSPI 1
+
+source [find target/stm32l4x.cfg]
+
+# QUADSPI initialization
+proc qspi_init { } {
+	global a
+	mmw 0x4002104C 0x000001FF 0				;# RCC_AHB2ENR |= GPIOAEN-GPIOIEN (enable clocks)
+	mmw 0x40021050 0x00000100 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PB11: BK1_NCS, PA03: CLK, PA06: BK1_IO3, PA07: BK1_IO2, PB00: BK1_IO1, PB01: BK1_IO0
+
+	# PA07:AF10:V, PA06:AF10:V, PA03:AF10:V, PB11:AF10:V, PB01:AF10:V, PB00:AF10:V
+
+	# Port A: PA07:AF10:V, PA06:AF10:V, PA03:AF10:V
+	mmw 0x48000000 0x0000A080 0x00005040    ;# MODER
+	mmw 0x48000008 0x0000F0C0 0x00000000    ;# OSPEEDR
+	mmw 0x48000020 0xAA00A000 0x55005000    ;# AFRL
+
+	# Port B: PB11:AF10:V, PB01:AF10:V, PB00:AF10:V
+	mmw 0x48000400 0x0080000A 0x00400005    ;# MODER
+	mmw 0x48000408 0x00C0000F 0x00000000    ;# OSPEEDR
+	mmw 0x48000420 0x000000AA 0x00000055    ;# AFRL
+	mmw 0x48000424 0x0000A000 0x00005000    ;# AFRH
+
+	mww 0xA0001030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x01500008				;# QUADSPI_CR: PRESCALER=1, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
+	mww 0xA0001004 0x00160100				;# QUADSPI_DCR: FSIZE=0x16, CSHT=0x01, CKMODE=0
+	mmw 0xA0001000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# 1-line spi mode
+	mww 0xA0001014 0x000003F5				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
+	sleep 1
+
+	# memory-mapped read mode with 3-byte addresses
+	mww 0xA0001014 0x0D002503				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
+}
+
+$_TARGETNAME configure -event reset-init {
+	mmw 0x40022000 0x00000004 0x00000003	;# 4 WS for 72 MHz HCLK
+	sleep 1
+	mmw 0x40021000 0x00000100 0x00000000	;# HSI on
+	mww 0x4002100C 0x01002432				;# 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI
+	mww 0x40021008 0x00008001				;# always HSI, APB1: /1, APB2: /1
+	mmw 0x40021000 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40021008 0x00000003 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 4000
+
+	qspi_init
+}
diff --git a/tcl/board/stm32l4p5g-disco.cfg b/tcl/board/stm32l4p5g-disco.cfg
new file mode 100644
index 0000000..d7420ed
--- /dev/null
+++ b/tcl/board/stm32l4p5g-disco.cfg
@@ -0,0 +1,130 @@
+# This is a STM32L4P5G discovery board with a single STM32L4R9AGI6 chip.
+# http://www.st.com/en/evaluation-tools/stm32l4p5g-dk.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select hla_swd
+
+# increase working area to 96KB
+set WORKAREASIZE 0x18000
+
+# enable stmqspi
+set OCTOSPI1 1
+set OCTOSPI2 0
+
+source [find target/stm32l4x.cfg]
+
+# OCTOSPI initialization
+# octo: 8-line mode
+proc octospi_init { octo } {
+	global a b
+	mmw 0x4002104C 0x001001FF 0				;# RCC_AHB2ENR |= OSPIMEN, GPIOAEN-GPIOIEN (enable clocks)
+	mmw 0x40021050 0x00000300 0				;# RCC_AHB3ENR |= OSPI2EN, OSPI1EN (enable clocks)
+	mmw 0x40021058 0x10000000 0				;# RCC_APB1ENR1 |= PWREN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	mmw 0x40007004 0x00000200 0				;# PWR_CR2 |= IOSV (required for use of GPOIG, cf. RM0432)
+
+	mww 0x50061C04 0x07050333				;# OCTOSPIM_P1CR: assign Port 1 to OCTOSPI2
+	mww 0x50061C08 0x03010111				;# OCTOSPIM_P2CR: assign Port 2 to OCTOSPI1
+
+	# PE11: P1_NCS, PE10: P1_CLK, PG06: P1_DQS, PD07: P1_IO7, PC03: P1_IO6, PD05: P1_IO5
+	# PD04: P1_IO4, PA06: P1_IO3, PA07: P1_IO2, PE13: P1_IO1, PE11: P1_IO0
+
+	# PA07:AF10:V, PA06:AF10:V, PC03:AF10:V, PD07:AF10:V, PD05:AF10:V, PD04:AF10:V
+	# PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V, PG06:AF03:V
+
+	# Port A: PA07:AF10:V, PA06:AF10:V
+	mmw 0x48000000 0x0000A000 0x00005000	;# MODER
+	mmw 0x48000008 0x0000F000 0x00000000	;# OSPEEDR
+	mmw 0x4800000C 0x00000000 0x0000F000	;# PUPDR
+	mmw 0x48000020 0xAA000000 0x55000000	;# AFRL
+	# Port C: PC03:AF10:V
+	mmw 0x48000800 0x00000080 0x00000040	;# MODER
+	mmw 0x48000808 0x000000C0 0x00000000	;# OSPEEDR
+	mmw 0x4800080C 0x00000000 0x000000C0	;# PUPDR
+	mmw 0x48000820 0x0000A000 0x00005000	;# AFRL
+	# Port D: PD07:AF10:V, PD05:AF10:V, PD04:AF10:V
+	mmw 0x48000C00 0x00008A00 0x00004500	;# MODER
+	mmw 0x48000C08 0x0000CF00 0x00000000	;# OSPEEDR
+	mmw 0x48000C0C 0x00000000 0x0000CF00	;# PUPDR
+	mmw 0x48000C20 0xA0AA0000 0x50550000	;# AFRL
+	# Port E: PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V
+	mmw 0x48001000 0x0AA00000 0x05500000	;# MODER
+	mmw 0x48001008 0x0FF00000 0x00000000	;# OSPEEDR
+	mmw 0x4800100C 0x00000000 0x0FF00000	;# PUPDR
+	mmw 0x48001024 0x00AAAA00 0x00555500	;# AFRH
+	# Port G: PG06:AF03:V
+	mmw 0x48001800 0x00002000 0x00001000	;# MODER
+	mmw 0x48001808 0x00003000 0x00000000	;# OSPEEDR
+	mmw 0x4800180C 0x00000000 0x00003000	;# PUPDR
+	mmw 0x48001820 0x03000000 0x0C000000	;# AFRL
+
+	# PG12: P2_NCS, PF04: P2_CLK, PF12: P2_DQS, PG10: P2_IO7, PG09: P2_IO6, PG01: P2_IO5
+	# PG00: P2_IO4, PF03: P2_IO3, PF02: P2_IO2, PF01: P2_IO1, PF00: P2_IO0
+
+	# PF12:AF05:V, PF04:AF05:V, PF03:AF05:V, PF02:AF05:V, PF01:AF05:V, PF00:AF05:V
+	# PG12:AF05:V, PG10:AF05:V, PG09:AF05:V, PG01:AF05:V, PG00:AF05:V
+
+	# Port F: PF12:AF05:V, PF04:AF05:V, PF03:AF05:V, PF02:AF05:V, PF01:AF05:V, PF00:AF05:V
+	mmw 0x48001400 0x020002AA 0x01000155	;# MODER
+	mmw 0x48001408 0x030003FF 0x00000000	;# OSPEEDR
+	mmw 0x4800140C 0x00000000 0x030003FF	;# PUPDR
+	mmw 0x48001420 0x00055555 0x000AAAAA	;# AFRL
+	mmw 0x48001424 0x00050000 0x000A0000	;# AFRH
+	# Port G: PG12:AF05:V, PG10:AF05:V, PG09:AF05:V, PG01:AF05:V, PG00:AF05:V
+	mmw 0x48001800 0x0228000A 0x01140005	;# MODER
+	mmw 0x48001808 0x033C000F 0x00000000	;# OSPEEDR
+	mmw 0x4800180C 0x00000000 0x033C000F	;# PUPDR
+	mmw 0x48001820 0x00000055 0x000000AA	;# AFRL
+	mmw 0x48001824 0x00050550 0x000A0AA0	;# AFRH
+
+	# OCTOSPI1: memory-mapped 1-line read mode with 4-byte addresses
+	mww 0xA0001130 0x00001000				;# OCTOSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x3040000B				;# OCTOSPI_CR: FMODE=0x1, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=0
+	mww 0xA0001008 0x01190100				;# OCTOSPI_DCR1: MTYP=0x1, FSIZE=0x19, CSHT=0x01, CKMODE=0, DLYBYP=0
+	mww 0xA000100C 0x00000001				;# OCTOSPI_DCR2: PRESCALER=1
+
+	mww 0xA0001108 0x00000000				;# OCTOSPI_TCR: SSHIFT=0, DHQC=0, DCYC=0x0
+	mww 0xA0001100 0x01003101				;# OCTOSPI_CCR: DMODE=0x1, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x1, ISIZE=0x0, IMODE=0x1
+	mww 0xA0001110 0x00000013				;# OCTOSPI_IR: INSTR=READ4B
+
+	if { $octo == 1 } {
+		stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00			;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
+		stmqspi cmd $a 0 0x06								;# Write Enable
+		stmqspi cmd $a 1 0x05								;# Read Status Register
+		stmqspi cmd $a 0 0x72 0x00 0x00 0x00 0x00 0x02		;# Write Conf. Reg. 2, addr 0x00000000: DTR OPI enable
+
+		# OCTOSPI1: memory-mapped 8-line read mode with 4-byte addresses
+		mww 0xA0001000 0x3040000B				;# OCTOSPI_CR: FMODE=0x3, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=1, EN=1
+		mww 0xA0001108 0x10000006				;# OCTOSPI_TCR: SSHIFT=0, DHQC=1, DCYC=0x6
+		mww 0xA0001100 0x2C003C1C				;# OCTOSPI_CCR: DTR, DMODE=0x4, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x4, ISIZE=0x1, IMODE=0x4
+		mww 0xA0001110 0x0000EE11				;# OCTOSPI_IR: INSTR=OCTA DTR Read
+
+		flash probe $a							;# reload configuration from CR, TCR, CCR, IR register values
+
+		stmqspi cmd $a 0 0x06								;# Write Enable
+		stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00			;# Read Status Register (note dummy address in 8-line mode)
+		stmqspi cmd $a 0 0x04								;# Write Disable
+		stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00			;# Read Status Register (note dummy address in 8-line mode)
+		stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00			;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
+	}
+}
+
+$_TARGETNAME configure -event reset-init {
+	mmw 0x40022000 0x00000003 0x0000000C	;# 3 WS for 72 MHz HCLK
+	sleep 1
+	mmw 0x40021000 0x00000100 0x00000000	;# HSI on
+	mww 0x4002100C 0x01002432				;# RCC_PLLCFGR 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI
+	mww 0x40021008 0x00008001				;# always HSI, APB1: /1, APB2: /1
+	mmw 0x40021000 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40021008 0x00000003 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 24000
+
+	octospi_init 1
+}
+
diff --git a/tcl/board/stm32l4r9i-disco.cfg b/tcl/board/stm32l4r9i-disco.cfg
new file mode 100644
index 0000000..70ed199
--- /dev/null
+++ b/tcl/board/stm32l4r9i-disco.cfg
@@ -0,0 +1,100 @@
+# This is a STM32L4R9I discovery board with a single STM32L4R9AII6 chip.
+# http://www.st.com/en/evaluation-tools/32l4r9idiscovery.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select hla_swd
+
+# increase working area to 96KB
+set WORKAREASIZE 0x18000
+
+# enable stmqspi
+set OCTOSPI1 1
+set OCTOSPI2 0
+
+source [find target/stm32l4x.cfg]
+
+# OCTOSPI initialization
+# octo: 8-line mode
+proc octospi_init { octo } {
+	global a b
+	mmw 0x4002104C 0x001001FF 0				;# RCC_AHB2ENR |= OSPIMEN, GPIOAEN-GPIOIEN (enable clocks)
+	mmw 0x40021050 0x00000300 0				;# RCC_AHB3ENR |= OSPI2EN, OSPI1EN (enable clocks)
+	mmw 0x40021058 0x10000000 0				;# RCC_APB1ENR1 |= PWREN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	mmw 0x40007004 0x00000200 0				;# PWR_CR2 |= IOSV (required for use of GPOIG, cf. RM0432)
+
+	mww 0x50061C04 0x00000000				;# OCTOSPIM_P1CR: disable Port 1
+	mww 0x50061C08 0x03010111				;# OCTOSPIM_P2CR: assign Port 2 to OCTOSPI1
+
+	# PG12: P2_NCS, PI06: P2_CLK, PG15: P2_DQS, PG10: P2_IO7, PG09: P2_IO6, PH10: P2_IO5,
+	# PH09: P2_IO4, PH08: P2_IO3, PI09: P2_IO2, PI10: P2_IO1, PI11: P2_IO0
+
+	# PG15:AF05:V, PG12:AF05:V, PG10:AF05:V, PG09:AF05:V, PH10:AF05:V, PH09:AF05:V
+	# PH08:AF05:V, PI11:AF05:V, PI10:AF05:V, PI09:AF05:V, PI06:AF05:V
+
+	# Port G: PG15:AF05:V, PG12:AF05:V, PG10:AF05:V, PG09:AF05:V
+	mmw 0x48001800 0x82280000 0x41140000	;# MODER
+	mmw 0x48001808 0xC33C0000 0x00000000	;# OSPEEDR
+	mmw 0x48001824 0x50050550 0xA00A0AA0	;# AFRH
+
+	# Port H: PH10:AF05:V, PH09:AF05:V, PH08:AF05:V
+	mmw 0x48001C00 0x002A0000 0x00150000	;# MODER
+	mmw 0x48001C08 0x003F0000 0x00000000	;# OSPEEDR
+	mmw 0x48001C24 0x00000555 0x00000AAA	;# AFRH
+
+	# Port I: PI11:AF05:V, PI10:AF05:V, PI09:AF05:V, PI06:AF05:V
+	mmw 0x48002000 0x00A82000 0x00541000	;# MODER
+	mmw 0x48002008 0x00FC3000 0x00000000	;# OSPEEDR
+	mmw 0x48002020 0x05000000 0x0A000000	;# AFRL
+	mmw 0x48002024 0x00005550 0x0000AAA0	;# AFRH
+
+	# OCTOSPI1: memory-mapped 1-line read mode with 4-byte addresses
+	mww 0xA0001130 0x00001000				;# OCTOSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x3040000B				;# OCTOSPI_CR: FMODE=0x1, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=0
+	mww 0xA0001008 0x01190100				;# OCTOSPI_DCR1: MTYP=0x1, FSIZE=0x19, CSHT=0x01, CKMODE=0, DLYBYP=0
+	mww 0xA000100C 0x00000001				;# OCTOSPI_DCR2: PRESCALER=1
+
+	mww 0xA0001108 0x00000000				;# OCTOSPI_TCR: SSHIFT=0, DHQC=0, DCYC=0x0
+	mww 0xA0001100 0x01003101				;# OCTOSPI_CCR: DMODE=0x1, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x1, ISIZE=0x0, IMODE=0x1
+	mww 0xA0001110 0x00000013				;# OCTOSPI_IR: INSTR=READ4B
+
+	if { $octo == 1 } {
+		stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00			;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
+		stmqspi cmd $a 0 0x06								;# Write Enable
+		stmqspi cmd $a 1 0x05								;# Read Status Register
+		stmqspi cmd $a 0 0x72 0x00 0x00 0x00 0x00 0x02		;# Write Conf. Reg. 2, addr 0x00000000: DTR OPI enable
+
+		# OCTOSPI1: memory-mapped 8-line read mode with 4-byte addresses
+		mww 0xA0001000 0x3040000B				;# OCTOSPI_CR: FMODE=0x3, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=1, EN=1
+		mww 0xA0001108 0x10000006				;# OCTOSPI_TCR: SSHIFT=0, DHQC=1, DCYC=0x6
+		mww 0xA0001100 0x2C003C1C				;# OCTOSPI_CCR: DTR, DMODE=0x4, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x4, ISIZE=0x1, IMODE=0x4
+		mww 0xA0001110 0x0000EE11				;# OCTOSPI_IR: INSTR=OCTA DTR Read
+
+		flash probe $a							;# reload configuration from CR, TCR, CCR, IR register values
+
+		stmqspi cmd $a 0 0x06								;# Write Enable
+		stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00			;# Read Status Register (note dummy address in 8-line mode)
+		stmqspi cmd $a 0 0x04								;# Write Disable
+		stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00			;# Read Status Register (note dummy address in 8-line mode)
+		stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00			;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
+	}
+}
+
+$_TARGETNAME configure -event reset-init {
+	mmw 0x40022000 0x00000003 0x0000000C	;# 3 WS for 72 MHz HCLK
+	sleep 1
+	mmw 0x40021000 0x00000100 0x00000000	;# HSI on
+	mww 0x4002100C 0x01002432				;# RCC_PLLCFGR 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI
+	mww 0x40021008 0x00008001				;# always HSI, APB1: /1, APB2: /1
+	mmw 0x40021000 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40021008 0x00000003 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 4000
+
+	octospi_init 1
+}
diff --git a/tcl/target/stm32f4x.cfg b/tcl/target/stm32f4x.cfg
index b95e783..1587533 100644
--- a/tcl/target/stm32f4x.cfg
+++ b/tcl/target/stm32f4x.cfg
@@ -52,6 +52,12 @@ flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
 
 flash bank $_CHIPNAME.otp stm32f2x 0x1fff7800 0 0 0 $_TARGETNAME
 
+if { [info exists QUADSPI] && $QUADSPI } {
+   set a [llength [flash list]]
+   set _QSPINAME $_CHIPNAME.qspi
+   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
+}
+
 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
 #
 # Since we may be running of an RC oscilator, we crank down the speed a
diff --git a/tcl/target/stm32f7x.cfg b/tcl/target/stm32f7x.cfg
index 6ad4b65..3c7679d 100644
--- a/tcl/target/stm32f7x.cfg
+++ b/tcl/target/stm32f7x.cfg
@@ -12,7 +12,7 @@ if { [info exists CHIPNAME] } {
    set _CHIPNAME stm32f7x
 }
 
-   set _ENDIAN little
+set _ENDIAN little
 
 # Work-area is a space in RAM used for flash programming
 # By default use 128kB
@@ -64,6 +64,12 @@ flash bank $_CHIPNAME.otp stm32f2x 0x1ff0f000 0 0 0 $_TARGETNAME
 #     the Flash via ITCM alias as virtual
 flash bank $_CHIPNAME.itcm-flash.alias virtual 0x00200000 0 0 0 $_TARGETNAME $_FLASHNAME
 
+if { [info exists QUADSPI] && $QUADSPI } {
+   set a [llength [flash list]]
+   set _QSPINAME $_CHIPNAME.qspi
+   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
+}
+
 # adapter speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
 adapter speed 2000
 
diff --git a/tcl/target/stm32h7x.cfg b/tcl/target/stm32h7x.cfg
index 763a785..8258e50 100644
--- a/tcl/target/stm32h7x.cfg
+++ b/tcl/target/stm32h7x.cfg
@@ -104,6 +104,23 @@ if {[set $_CHIPNAME.DUAL_CORE]} {
 # Make sure that cpu0 is selected
 targets $_CHIPNAME.cpu0
 
+if { [info exists QUADSPI] && $QUADSPI } {
+   set a [llength [flash list]]
+   set _QSPINAME $_CHIPNAME.qspi
+   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_CHIPNAME.cpu0 0x52005000
+} else {
+   if { [info exists OCTOSPI1] && $OCTOSPI1 } {
+      set a [llength [flash list]]
+      set _OCTOSPINAME1 $_CHIPNAME.octospi1
+      flash bank $_OCTOSPINAME1 stmqspi 0x90000000 0 0 0 $_CHIPNAME.cpu0 0x52005000
+   }
+   if { [info exists OCTOSPI2] && $OCTOSPI2 } {
+      set b [llength [flash list]]
+      set _OCTOSPINAME2 $_CHIPNAME.octospi2
+      flash bank $_OCTOSPINAME2 stmqspi 0x70000000 0 0 0 $_CHIPNAME.cpu0 0x5200A000
+   }
+}
+
 # Clock after reset is HSI at 64 MHz, no need of PLL
 adapter speed 1800
 
diff --git a/tcl/target/stm32l4x.cfg b/tcl/target/stm32l4x.cfg
index 46e6f7e..7f08f3c 100644
--- a/tcl/target/stm32l4x.cfg
+++ b/tcl/target/stm32l4x.cfg
@@ -50,6 +50,23 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
 
+if { [info exists QUADSPI] && $QUADSPI } {
+   set a [llength [flash list]]
+   set _QSPINAME $_CHIPNAME.qspi
+   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
+} else {
+   if { [info exists OCTOSPI1] && $OCTOSPI1 } {
+      set a [llength [flash list]]
+      set _OCTOSPINAME1 $_CHIPNAME.octospi1
+      flash bank $_OCTOSPINAME1 stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
+   }
+   if { [info exists OCTOSPI2] && $OCTOSPI2 } {
+      set b [llength [flash list]]
+      set _OCTOSPINAME2 $_CHIPNAME.octospi2
+      flash bank $_OCTOSPINAME2 stmqspi 0x70000000 0 0 0 $_TARGETNAME 0xA0001400
+   }
+}
+
 # Common knowledges tells JTAG speed should be <= F_CPU/6.
 # F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
 # the safe side.