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| author | Marc Schink <dev@zapb.de> | 2023-11-08 10:27:36 +0100 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2023-12-30 13:14:39 +0000 |
| commit | b0f99dfed0d0f95d3f9190f1767b4f2f6969f5bc (patch) | |
| tree | 813a3511ed6cf7fa0eb535752dc0302b58edf234 /tcl | |
| parent | 7f3aba13191debc68742f70580de7cf8465d3611 (diff) | |
| download | riscv-openocd-b0f99dfed0d0f95d3f9190f1767b4f2f6969f5bc.zip riscv-openocd-b0f99dfed0d0f95d3f9190f1767b4f2f6969f5bc.tar.gz riscv-openocd-b0f99dfed0d0f95d3f9190f1767b4f2f6969f5bc.tar.bz2 | |
tcl/target: Add Geehy APM32F1x config
Tested with APM32F103CBT6 using JTAG and SWD transport. All flash
operations, including sector and device protection, work as expected.
Change-Id: Ibefe1a65d710aea87b86ab7ff8a4153512a0ea4f
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8017
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Diffstat (limited to 'tcl')
| -rw-r--r-- | tcl/target/geehy/apm32f1x.cfg | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/tcl/target/geehy/apm32f1x.cfg b/tcl/target/geehy/apm32f1x.cfg new file mode 100644 index 0000000..dc42e06 --- /dev/null +++ b/tcl/target/geehy/apm32f1x.cfg @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Geehy APM32F1x target +# +# https://global.geehy.com/MCU +# + +# +# APM32F1x devices support JTAG and SWD transport. +# +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME apm32f1x +} + +# Work-area is a space in RAM used for flash programming, by default use 4 KiB. +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x1000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + set _CPUTAPID 0x4ba00477 + } { + set _CPUTAPID 0x2ba01477 + } +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +if {[using_jtag]} { + jtag newtap $_CHIPNAME bs -irlen 5 +} + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME + +adapter speed 1000 + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to perform a soft reset. + cortex_m reset_config sysresetreq +} |