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| author | Marc Schink <dev@zapb.de> | 2023-05-14 15:03:07 +0200 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2023-12-30 13:14:17 +0000 |
| commit | 7f3aba13191debc68742f70580de7cf8465d3611 (patch) | |
| tree | fab45047952059ee67fea4d0d9de6f2ffff86714 /tcl | |
| parent | d46a3d635e3d41e2c531a20c97bde217431b5f76 (diff) | |
| download | riscv-openocd-7f3aba13191debc68742f70580de7cf8465d3611.zip riscv-openocd-7f3aba13191debc68742f70580de7cf8465d3611.tar.gz riscv-openocd-7f3aba13191debc68742f70580de7cf8465d3611.tar.bz2 | |
tcl/target: Add Geehy APM32F4x config
Tested with APM32407RGT6 using JTAG and SWD transport. All flash
operations, including sector and device protection, work as expected.
Revision identifier (0x0009) is not updated due to missing documentation.
Change-Id: I33f4630fd00096656369ecc923aea2dcad77c7d3
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8016
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'tcl')
| -rw-r--r-- | tcl/target/geehy/apm32f4x.cfg | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/tcl/target/geehy/apm32f4x.cfg b/tcl/target/geehy/apm32f4x.cfg new file mode 100644 index 0000000..3ed58d1 --- /dev/null +++ b/tcl/target/geehy/apm32f4x.cfg @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Geehy APM32F4x target +# +# https://global.geehy.com/MCU +# + +# +# APM32F4x devices support JTAG and SWD transport. +# +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME apm32f4x +} + +# Work-area is a space in RAM used for flash programming, by default use 4 KiB. +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x1000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + set _CPUTAPID 0x4ba00477 + } else { + set _CPUTAPID 0x2ba01477 + } +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +if { [using_jtag] } { + jtag newtap $_CHIPNAME bs -irlen 5 +} + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME + +adapter speed 1000 + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to perform a soft reset. + cortex_m reset_config sysresetreq +} |