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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2011-10-29 23:32:17 +0200 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2011-11-07 16:16:33 +0000 |
| commit | ca45e700b1c57caca2ef08e665e3c7e3e02ac8d3 (patch) | |
| tree | b3a745550c44fbac2101d25ae89be31e5e10631c /tcl/target/ti_dm365.cfg | |
| parent | 17b546a900f2215d26cfdafa6938d814c0ab4ec3 (diff) | |
| download | riscv-openocd-ca45e700b1c57caca2ef08e665e3c7e3e02ac8d3.zip riscv-openocd-ca45e700b1c57caca2ef08e665e3c7e3e02ac8d3.tar.gz riscv-openocd-ca45e700b1c57caca2ef08e665e3c7e3e02ac8d3.tar.bz2 | |
target config files: Fix whitespace issues.
Drop useless double-space occurences, drop trailing whitespace, and fix
some other minor whitespace-related issues.
Change-Id: I6b4c515492e2ee94dc25ef1fe4f51015a4bba8b5
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/137
Tested-by: jenkins
Diffstat (limited to 'tcl/target/ti_dm365.cfg')
| -rw-r--r-- | tcl/target/ti_dm365.cfg | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/tcl/target/ti_dm365.cfg b/tcl/target/ti_dm365.cfg index e2d29bd..a260278 100644 --- a/tcl/target/ti_dm365.cfg +++ b/tcl/target/ti_dm365.cfg @@ -1,10 +1,10 @@ # -# Texas Instruments DaVinci family: TMS320DM365 +# Texas Instruments DaVinci family: TMS320DM365 # if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME dm365 + set _CHIPNAME dm365 } # TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled* @@ -18,7 +18,7 @@ set EMU01 "-disable" source [find target/icepick.cfg] # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer -if { [info exists ETB_TAPID ] } { +if { [info exists ETB_TAPID] } { set _ETB_TAPID $ETB_TAPID } else { set _ETB_TAPID 0x2b900f0f @@ -28,7 +28,7 @@ jtag configure $_CHIPNAME.etb -event tap-enable \ "icepick_c_tapenable $_CHIPNAME.jrc 1" # Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM. -if { [info exists CPU_TAPID ] } { +if { [info exists CPU_TAPID] } { set _CPU_TAPID $CPU_TAPID } else { set _CPU_TAPID 0x0792602f @@ -38,7 +38,7 @@ jtag configure $_CHIPNAME.arm -event tap-enable \ "icepick_c_tapenable $_CHIPNAME.jrc 0" # Primary TAP: ICEpick (JTAG route controller) and boundary scan -if { [info exists JRC_TAPID ] } { +if { [info exists JRC_TAPID] } { set _JRC_TAPID $JRC_TAPID } else { set _JRC_TAPID 0x0b83e02f @@ -73,7 +73,7 @@ dict set dm365 ddr 0x80000000 source [find target/davinci.cfg] ################ -# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K) +# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K) # and the ETB memory (4K) are other options, while trace is unused. set _TARGETNAME $_CHIPNAME.arm |