diff options
| author | Uwe Hermann <uwe@hermann-uwe.de> | 2011-10-29 23:32:17 +0200 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2011-11-07 16:16:33 +0000 |
| commit | ca45e700b1c57caca2ef08e665e3c7e3e02ac8d3 (patch) | |
| tree | b3a745550c44fbac2101d25ae89be31e5e10631c /tcl/target | |
| parent | 17b546a900f2215d26cfdafa6938d814c0ab4ec3 (diff) | |
| download | riscv-openocd-ca45e700b1c57caca2ef08e665e3c7e3e02ac8d3.zip riscv-openocd-ca45e700b1c57caca2ef08e665e3c7e3e02ac8d3.tar.gz riscv-openocd-ca45e700b1c57caca2ef08e665e3c7e3e02ac8d3.tar.bz2 | |
target config files: Fix whitespace issues.
Drop useless double-space occurences, drop trailing whitespace, and fix
some other minor whitespace-related issues.
Change-Id: I6b4c515492e2ee94dc25ef1fe4f51015a4bba8b5
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/137
Tested-by: jenkins
Diffstat (limited to 'tcl/target')
78 files changed, 491 insertions, 496 deletions
diff --git a/tcl/target/aduc702x.cfg b/tcl/target/aduc702x.cfg index dcb9c12..f06dc33 100644 --- a/tcl/target/aduc702x.cfg +++ b/tcl/target/aduc702x.cfg @@ -1,20 +1,20 @@ if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME aduc702x + set _CHIPNAME aduc702x } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - # This config file was defaulting to big endian.. - set _ENDIAN little + # This config file was defaulting to big endian.. + set _ENDIAN little } if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID + set _CPUTAPID $CPUTAPID } else { - set _CPUTAPID 0x3f0f0f0f + set _CPUTAPID 0x3f0f0f0f } adapter_nsrst_delay 200 diff --git a/tcl/target/amdm37x.cfg b/tcl/target/amdm37x.cfg index b1bd25c..3121e8f 100644 --- a/tcl/target/amdm37x.cfg +++ b/tcl/target/amdm37x.cfg @@ -21,9 +21,9 @@ if { [info exists CHIPTYPE] } { if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME $CHIPTYPE + set _CHIPNAME $CHIPTYPE } switch $CHIPTYPE { diff --git a/tcl/target/at91r40008.cfg b/tcl/target/at91r40008.cfg index 9c0c483..2d286ab 100644 --- a/tcl/target/at91r40008.cfg +++ b/tcl/target/at91r40008.cfg @@ -5,19 +5,19 @@ reset_config srst_only srst_pulls_trst if {[info exists CHIPNAME]} { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME at91r40008 + set _CHIPNAME at91r40008 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } # Setup the JTAG scan chain. -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x1f0f0f0f diff --git a/tcl/target/at91rm9200.cfg b/tcl/target/at91rm9200.cfg index a9cda19..2e8c1e0 100644 --- a/tcl/target/at91rm9200.cfg +++ b/tcl/target/at91rm9200.cfg @@ -2,18 +2,18 @@ # http://atmel.com/products/at91/ if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME at91rm9200 + set _CHIPNAME at91rm9200 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x05b0203f diff --git a/tcl/target/at91sam3XXX.cfg b/tcl/target/at91sam3XXX.cfg index 517a871..a13e399 100644 --- a/tcl/target/at91sam3XXX.cfg +++ b/tcl/target/at91sam3XXX.cfg @@ -18,20 +18,19 @@ # at91sam3s1a if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME sam3 + set _CHIPNAME sam3 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } - #jtag scan chain -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x4ba00477 diff --git a/tcl/target/at91sam3nXX.cfg b/tcl/target/at91sam3nXX.cfg index 5392824..9e362b2 100644 --- a/tcl/target/at91sam3nXX.cfg +++ b/tcl/target/at91sam3nXX.cfg @@ -9,7 +9,7 @@ if { [info exists CHIPNAME] } { set _CHIPNAME at91sam3n } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x4ba00477 diff --git a/tcl/target/at91sam7se512.cfg b/tcl/target/at91sam7se512.cfg index 7273a06..17d0d8e 100644 --- a/tcl/target/at91sam7se512.cfg +++ b/tcl/target/at91sam7se512.cfg @@ -1,21 +1,20 @@ - # ATMEL sam7se512 # Example: the "Elektor Internet Radio" - EIR # http://www.ethernut.de/en/hardware/eir/index.html if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME sam7se512 + set _CHIPNAME sam7se512 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { # Force an error until we get a good number. diff --git a/tcl/target/at91sam7sx.cfg b/tcl/target/at91sam7sx.cfg index 6cbd6b6..20e4689 100644 --- a/tcl/target/at91sam7sx.cfg +++ b/tcl/target/at91sam7sx.cfg @@ -2,18 +2,18 @@ reset_config srst_only srst_pulls_trst if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME at91sam7s + set _CHIPNAME at91sam7s } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x3f0f0f0f diff --git a/tcl/target/at91sam7x256.cfg b/tcl/target/at91sam7x256.cfg index dd36458..d1bfc77 100644 --- a/tcl/target/at91sam7x256.cfg +++ b/tcl/target/at91sam7x256.cfg @@ -2,18 +2,18 @@ reset_config srst_only srst_pulls_trst if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME sam7x256 + set _CHIPNAME sam7x256 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x3f0f0f0f diff --git a/tcl/target/at91sam9.cfg b/tcl/target/at91sam9.cfg index 08154ce..e6b297d 100644 --- a/tcl/target/at91sam9.cfg +++ b/tcl/target/at91sam9.cfg @@ -14,7 +14,7 @@ if { [info exists ENDIAN] } { set _ENDIAN little } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x0792603f diff --git a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg index 8df2852..f7121ec 100644 --- a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg +++ b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg @@ -27,7 +27,7 @@ flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME # Faster memory downloads. This is disabled automatically during # reset init since all reset init sequences are too short for # fast memory access -arm7_9 dcc_downloads enable +arm7_9 dcc_downloads enable arm7_9 fast_memory_access enable proc at91sam_init { } { diff --git a/tcl/target/at91sam9rl.cfg b/tcl/target/at91sam9rl.cfg index 769c4f7..db05229 100644 --- a/tcl/target/at91sam9rl.cfg +++ b/tcl/target/at91sam9rl.cfg @@ -3,9 +3,9 @@ ###################################### if { [info exists CHIPNAME] } { - set AT91_CHIPNAME $CHIPNAME + set AT91_CHIPNAME $CHIPNAME } else { - set AT91_CHIPNAME at91sam9rl + set AT91_CHIPNAME at91sam9rl } source [find target/at91sam9.cfg] diff --git a/tcl/target/atmega128.cfg b/tcl/target/atmega128.cfg index 212a267..b8f7d01 100644 --- a/tcl/target/atmega128.cfg +++ b/tcl/target/atmega128.cfg @@ -1,16 +1,16 @@ # for avr - set _CHIPNAME avr - set _ENDIAN little + set _CHIPNAME avr + set _ENDIAN little # jtag speed adapter_khz 4500 -reset_config srst_only +reset_config srst_only adapter_nsrst_delay 100 #jtag scan chain -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x8970203F diff --git a/tcl/target/avr32.cfg b/tcl/target/avr32.cfg index 1a2ea33..932b750 100644 --- a/tcl/target/avr32.cfg +++ b/tcl/target/avr32.cfg @@ -1,7 +1,7 @@ -set _CHIPNAME avr32 -set _ENDIAN big +set _CHIPNAME avr32 +set _ENDIAN big -set _CPUTAPID 0x21e8203f +set _CPUTAPID 0x21e8203f jtag_nsrst_delay 100 jtag_ntrst_delay 100 @@ -10,7 +10,7 @@ reset_config trst_and_srst separate # jtag scan chain # format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_CPUTAPID +jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_CPUTAPID set _TARGETNAME [format "%s.cpu" $_CHIPNAME] target create $_TARGETNAME avr32_ap7k -endian $_ENDIAN -chain-position $_TARGETNAME diff --git a/tcl/target/c100.cfg b/tcl/target/c100.cfg index 23eca0c..1eaa8fe 100644 --- a/tcl/target/c100.cfg +++ b/tcl/target/c100.cfg @@ -6,24 +6,24 @@ adapter_khz 100 if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME c100 + set _CHIPNAME c100 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x27b3645b } -if { [info exists DSPTAPID ] } { +if { [info exists DSPTAPID] } { set _DSPTAPID $DSPTAPID } else { set _DSPTAPID 0x27b3645b diff --git a/tcl/target/cs351x.cfg b/tcl/target/cs351x.cfg index 243f963..0785d53 100644 --- a/tcl/target/cs351x.cfg +++ b/tcl/target/cs351x.cfg @@ -1,22 +1,22 @@ if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME cs351x + set _CHIPNAME cs351x } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x00526fa1 } -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID # Create the GDB Target. set _TARGETNAME $_CHIPNAME.cpu @@ -24,7 +24,7 @@ target create $_TARGETNAME fa526 -endian $_ENDIAN -chain-position $_TARGETNAME - # There is 16K of SRAM on this chip # FIXME: flash programming is not working by using this work area. So comment this out for now. -#$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x4000 -work-area-backup 1 +#$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x4000 -work-area-backup 1 # This chip has a DCC ... use it arm7_9 dcc_downloads enable diff --git a/tcl/target/davinci.cfg b/tcl/target/davinci.cfg index 9e9369d..859a925 100644 --- a/tcl/target/davinci.cfg +++ b/tcl/target/davinci.cfg @@ -2,7 +2,7 @@ # Utility code for DaVinci-family chips # -# davinci_pinmux: assigns PINMUX$reg <== $value +# davinci_pinmux: assigns PINMUX$reg <== $value proc davinci_pinmux {soc reg value} { mww [expr [dict get $soc sysbase] + 4 * $reg] $value } @@ -20,13 +20,13 @@ source [find mem_helper.tcl] # # PLL version 0x02: tested on dm355 -# REVISIT: On dm6446/dm357 the PLLRST polarity is different. +# REVISIT: On dm6446/dm357 the PLLRST polarity is different. proc pll_v02_setup {pll_addr mult config} { set pll_ctrl_addr [expr $pll_addr + 0x100] set pll_ctrl [mrw $pll_ctrl_addr] # 1 - clear CLKMODE (bit 8) iff using on-chip oscillator - # NOTE: this assumes we should clear that bit + # NOTE: this assumes we should clear that bit set pll_ctrl [expr $pll_ctrl & ~0x0100] mww $pll_ctrl_addr $pll_ctrl @@ -57,8 +57,8 @@ proc pll_v02_setup {pll_addr mult config} { set pll_ctrl [expr $pll_ctrl & ~0x0010] mww $pll_ctrl_addr $pll_ctrl - # 9 - optional: write prediv, postdiv, and pllm - # NOTE: for dm355 PLL1, postdiv is controlled via MISC register + # 9 - optional: write prediv, postdiv, and pllm + # NOTE: for dm355 PLL1, postdiv is controlled via MISC register mww [expr $pll_addr + 0x0110] [expr ($mult - 1) & 0xff] if { [dict exists $config prediv] } { set div [dict get $config prediv] @@ -71,7 +71,7 @@ proc pll_v02_setup {pll_addr mult config} { mww [expr $pll_addr + 0x0128] $div } - # 10 - optional: set plldiv1, plldiv2, ... + # 10 - optional: set plldiv1, plldiv2, ... # NOTE: this assumes some registers have their just-reset values: # - PLLSTAT.GOSTAT is clear when we enter # - ALNCTL has everything set @@ -162,7 +162,7 @@ proc pll_v03_setup {pll_addr mult config} { set pll_ctrl [expr $pll_ctrl & ~0x0008] mww $pll_ctrl_addr $pll_ctrl - # 9 - optional: write prediv, postdiv, and pllm + # 9 - optional: write prediv, postdiv, and pllm mww [expr $pll_addr + 0x0110] [expr ($mult / 2) & 0x1ff] if { [dict exists $config prediv] } { set div [dict get $config prediv] @@ -181,8 +181,8 @@ proc pll_v03_setup {pll_addr mult config} { mww $pll_secctrl_addr 0x00400000 mww $pll_secctrl_addr 0x00410000 - # 11 - optional: set plldiv1, plldiv2, ... - # NOTE: this assumes some registers have their just-reset values: + # 11 - optional: set plldiv1, plldiv2, ... + # NOTE: this assumes some registers have their just-reset values: # - PLLSTAT.GOSTAT is clear when we enter set aln 0 if { [dict exists $config div1] } { @@ -283,7 +283,7 @@ proc pll_v03_setup {pll_addr mult config} { mww $pll_ctrl_addr $pll_ctrl } -# NOTE: dm6446 requires EMURSTIE set in MDCTL before certain +# NOTE: dm6446 requires EMURSTIE set in MDCTL before certain # modules can be enabled. # prepare a non-DSP module to be enabled; finish with psc_go diff --git a/tcl/target/dragonite.cfg b/tcl/target/dragonite.cfg index 7e85624..750fd64 100644 --- a/tcl/target/dragonite.cfg +++ b/tcl/target/dragonite.cfg @@ -3,18 +3,18 @@ ###################################### if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME dragonite + set _CHIPNAME dragonite } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x121003d3 diff --git a/tcl/target/dsp56321.cfg b/tcl/target/dsp56321.cfg index 74279d9..6f32223 100644 --- a/tcl/target/dsp56321.cfg +++ b/tcl/target/dsp56321.cfg @@ -2,19 +2,19 @@ # if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME dsp56321 + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME dsp56321 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { + set _ENDIAN $ENDIAN +} else { # this defaults to a big endian - set _ENDIAN big + set _ENDIAN big } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x1181501d diff --git a/tcl/target/dsp568013.cfg b/tcl/target/dsp568013.cfg index 2b25ed7..0c491fa 100644 --- a/tcl/target/dsp568013.cfg +++ b/tcl/target/dsp568013.cfg @@ -1,19 +1,19 @@ # Script for freescale DSP568013 if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME dsp568013 + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME dsp568013 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { + set _ENDIAN $ENDIAN +} else { # this defaults to a big endian - set _ENDIAN little + set _ENDIAN little } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x01f2401d @@ -60,11 +60,11 @@ jtag configure $_CHIPNAME.chp -event tap-enable " #disables the master tap jtag configure $_TARGETNAME -event tap-disable " " -#TODO FIND SMARTER WAY. +#TODO FIND SMARTER WAY. jtag configure $_CHIPNAME.chp -event tap-disable " " -#TODO FIND SMARTER WAY. +#TODO FIND SMARTER WAY. #working area at base of ram diff --git a/tcl/target/dsp568037.cfg b/tcl/target/dsp568037.cfg index 21eb0b7..01194d0 100644 --- a/tcl/target/dsp568037.cfg +++ b/tcl/target/dsp568037.cfg @@ -1,19 +1,19 @@ # Script for freescale DSP568037 -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME dsp568037 +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME dsp568037 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { # this defaults to a big endian - set _ENDIAN little + set _ENDIAN little } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x01f2801d @@ -56,11 +56,11 @@ jtag configure $_CHIPNAME.chp -event tap-enable " #disables the master tap jtag configure $_TARGETNAME -event tap-disable " " -#TODO FIND SMARTER WAY. +#TODO FIND SMARTER WAY. jtag configure $_CHIPNAME.chp -event tap-disable " " -#TODO FIND SMARTER WAY. +#TODO FIND SMARTER WAY. #working area at base of ram diff --git a/tcl/target/epc9301.cfg b/tcl/target/epc9301.cfg index 6b67b9d..f186d37 100644 --- a/tcl/target/epc9301.cfg +++ b/tcl/target/epc9301.cfg @@ -1,18 +1,18 @@ # Cirrus Logic EP9301 processor on an Olimex CS-E9301 board. if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME ep9301 + set _CHIPNAME ep9301 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { # Force an error until we get a good number. diff --git a/tcl/target/faux.cfg b/tcl/target/faux.cfg index b2bdb2b..fc905bf 100644 --- a/tcl/target/faux.cfg +++ b/tcl/target/faux.cfg @@ -1,18 +1,18 @@ #Script for faux target - used for testing if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME at91eb40a + set _CHIPNAME at91eb40a } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x00000000 diff --git a/tcl/target/feroceon.cfg b/tcl/target/feroceon.cfg index e90165b..389576e 100644 --- a/tcl/target/feroceon.cfg +++ b/tcl/target/feroceon.cfg @@ -3,18 +3,18 @@ ###################################### if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME feroceon + set _CHIPNAME feroceon } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x20a023d3 diff --git a/tcl/target/fm3.cfg b/tcl/target/fm3.cfg index af7647d..78df11b 100644 --- a/tcl/target/fm3.cfg +++ b/tcl/target/fm3.cfg @@ -2,18 +2,18 @@ # Fujitsu Cortex-M3 with 512kB Flash and 64kB RAM if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME mb9bf500 + set _CHIPNAME mb9bf500 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x4ba00477 diff --git a/tcl/target/hilscher_netx10.cfg b/tcl/target/hilscher_netx10.cfg index 14ff95d..3f96607 100644 --- a/tcl/target/hilscher_netx10.cfg +++ b/tcl/target/hilscher_netx10.cfg @@ -5,18 +5,18 @@ #Hilscher netX 10 CPU if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME netx10 + set _CHIPNAME netx10 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x25966021 diff --git a/tcl/target/hilscher_netx50.cfg b/tcl/target/hilscher_netx50.cfg index 1129544..c6510c6 100644 --- a/tcl/target/hilscher_netx50.cfg +++ b/tcl/target/hilscher_netx50.cfg @@ -5,18 +5,18 @@ #Hilscher netX 50 CPU if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME netx50 + set _CHIPNAME netx50 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x25966021 diff --git a/tcl/target/hilscher_netx500.cfg b/tcl/target/hilscher_netx500.cfg index 3b9e3d8..93375fd 100644 --- a/tcl/target/hilscher_netx500.cfg +++ b/tcl/target/hilscher_netx500.cfg @@ -1,18 +1,18 @@ #Hilscher netX 500 CPU if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME netx500 + set _CHIPNAME netx500 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x07926021 @@ -36,8 +36,8 @@ proc mread32 {addr} { proc sdram_fix { } { set accesskey [mread32 0x00100070] - mww 0x00100070 [expr $accesskey] - mww 0x0010002c 0x00000001 + mww 0x00100070 [expr $accesskey] + mww 0x0010002c 0x00000001 if {[expr [mread32 0x0010002c] & 0x07] == 0x07} { puts "SDRAM Fix was not executed. Probably your CPU halted too late and the register is already locked!" diff --git a/tcl/target/icepick.cfg b/tcl/target/icepick.cfg index ff73138..093d209 100644 --- a/tcl/target/icepick.cfg +++ b/tcl/target/icepick.cfg @@ -83,7 +83,7 @@ proc icepick_c_tapenable {jrc port} { # echo "Configuring the ICEpick" icepick_c_setup $jrc - # NOTE: it's important not to enter RUN/IDLE state until + # NOTE: it's important not to enter RUN/IDLE state until # done sending these instructions and data to the ICEpick. # And never to enter RESET, which will disable the TAPs. diff --git a/tcl/target/imx.cfg b/tcl/target/imx.cfg index 547ec56..9eea53e 100644 --- a/tcl/target/imx.cfg +++ b/tcl/target/imx.cfg @@ -1,6 +1,6 @@ # utility fn's for Freescale i.MX series -global TARGETNAME +global TARGETNAME set TARGETNAME $_TARGETNAME # rewrite commands of the form below to arm11 mcr... @@ -8,9 +8,9 @@ set TARGETNAME $_TARGETNAME proc setc15 {regs value} { global TARGETNAME - echo [format "set p15 0x%04x, 0x%08x" $regs $value] + echo [format "set p15 0x%04x, 0x%08x" $regs $value] - arm mcr 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value + arm mcr 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value } @@ -18,12 +18,12 @@ proc imx3x_reset {} { # this reset script comes from the Freescale PDK # # http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=IMX35PDK - + echo "Target Setup: initialize DRAM controller and peripherals" - + # Data.Set c15:0x01 %long 0x00050078 setc15 0x01 0x00050078 - + echo "configuring CP15 for enabling the peripheral bus" # Data.Set c15:0x042f %long 0x40000015 setc15 0x042f 0x40000015 diff --git a/tcl/target/imx21.cfg b/tcl/target/imx21.cfg index 410bce8..9a5e3ad 100644 --- a/tcl/target/imx21.cfg +++ b/tcl/target/imx21.cfg @@ -4,27 +4,27 @@ reset_config trst_and_srst if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME imx21 + set _CHIPNAME imx21 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } # Note above there is 1 tap # The CPU tap -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x0792611f } -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID # Create the GDB Target. diff --git a/tcl/target/imx25.cfg b/tcl/target/imx25.cfg index ead6610..bc91278 100644 --- a/tcl/target/imx25.cfg +++ b/tcl/target/imx25.cfg @@ -3,25 +3,25 @@ # if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME imx25 + set _CHIPNAME imx25 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } -if { [info exists ETBTAPID ] } { +if { [info exists ETBTAPID] } { set _ETBTAPID $ETBTAPID } else { set _ETBTAPID 0x1b900f0f } jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0x0f -expected-id $_ETBTAPID -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x07926041 @@ -30,7 +30,7 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0x0 -irmask 0x0 -expected-id 0x0 -if { [info exists SDMATAPID ] } { +if { [info exists SDMATAPID] } { set _SDMATAPID $SDMATAPID } else { set _SDMATAPID 0x0882301d diff --git a/tcl/target/imx27.cfg b/tcl/target/imx27.cfg index dabae6d..5530e68 100644 --- a/tcl/target/imx27.cfg +++ b/tcl/target/imx27.cfg @@ -7,42 +7,42 @@ reset_config trst_and_srst srst_pulls_trst if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME imx27 + set _CHIPNAME imx27 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } # Note above there are 2 taps # trace buffer -if { [info exists ETBTAPID ] } { +if { [info exists ETBTAPID] } { set _ETBTAPID $ETBTAPID } else { set _ETBTAPID 0x1b900f0f } -jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID +jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID # The CPU tap -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x07926121 } -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID # Create the GDB Target. set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs # REVISIT what operating environment sets up this virtual address mapping? $_TARGETNAME configure -work-area-virt 0xffff4c00 -work-area-phys 0xffff4c00 \ - -work-area-size 0x8000 -work-area-backup 1 + -work-area-size 0x8000 -work-area-backup 1 # Internal to the chip, there is 45K of SRAM # diff --git a/tcl/target/imx31.cfg b/tcl/target/imx31.cfg index b9eddd0..ca63951 100644 --- a/tcl/target/imx31.cfg +++ b/tcl/target/imx31.cfg @@ -6,30 +6,30 @@ reset_config trst_and_srst srst_gates_jtag adapter_nsrst_delay 5 if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME imx31 + set _CHIPNAME imx31 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x07b3601d } -if { [info exists SDMATAPID ] } { +if { [info exists SDMATAPID] } { set _SDMATAPID $SDMATAPID } else { set _SDMATAPID 0x2190101d } -if { [info exists ETBTAPID ] } { +if { [info exists ETBTAPID] } { set _ETBTAPID $ETBTAPID } else { set _ETBTAPID 0x2b900f0f diff --git a/tcl/target/imx35.cfg b/tcl/target/imx35.cfg index 8a6aa87..21495c2 100644 --- a/tcl/target/imx35.cfg +++ b/tcl/target/imx35.cfg @@ -5,30 +5,30 @@ reset_config trst_and_srst srst_gates_jtag jtag_ntrst_delay 100 if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME imx35 + set _CHIPNAME imx35 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x07b3601d } -if { [info exists SDMATAPID ] } { +if { [info exists SDMATAPID] } { set _SDMATAPID $SDMATAPID } else { set _SDMATAPID 0x0882601d } -if { [info exists ETBTAPID ] } { +if { [info exists ETBTAPID] } { set _ETBTAPID $ETBTAPID } else { set _ETBTAPID 0x2b900f0f diff --git a/tcl/target/imx51.cfg b/tcl/target/imx51.cfg index b1390ec..706875d 100644 --- a/tcl/target/imx51.cfg +++ b/tcl/target/imx51.cfg @@ -1,13 +1,13 @@ # Freescale i.MX51 if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME imx51 + set _CHIPNAME imx51 } # CoreSight Debug Access Port -if { [info exists DAP_TAPID ] } { +if { [info exists DAP_TAPID] } { set _DAP_TAPID $DAP_TAPID } else { set _DAP_TAPID 0x1ba00477 @@ -20,7 +20,7 @@ jtag newtap $_CHIPNAME DAP -irlen 4 -ircapture 0x1 -irmask 0xf \ jtag newtap $_CHIPNAME SDMA -irlen 4 -ircapture 0x0 -irmask 0xf # SJC -if { [info exists SJC_TAPID ] } { +if { [info exists SJC_TAPID] } { set _SJC_TAPID SJC_TAPID } else { set _SJC_TAPID 0x0190c01d @@ -29,7 +29,7 @@ if { [info exists SJC_TAPID ] } { jtag newtap $_CHIPNAME SJC -irlen 5 -ircapture 0x1 -irmask 0x1f \ -expected-id $_SJC_TAPID -ignore-version -# GDB target: Cortex-A8, using DAP +# GDB target: Cortex-A8, using DAP set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.DAP diff --git a/tcl/target/imx53.cfg b/tcl/target/imx53.cfg index b242fd6..7194783 100644 --- a/tcl/target/imx53.cfg +++ b/tcl/target/imx53.cfg @@ -1,13 +1,13 @@ # Freescale i.MX53 if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME imx53 + set _CHIPNAME imx53 } # CoreSight Debug Access Port -if { [info exists DAP_TAPID ] } { +if { [info exists DAP_TAPID] } { set _DAP_TAPID $DAP_TAPID } else { set _DAP_TAPID 0x1ba00477 @@ -20,7 +20,7 @@ jtag newtap $_CHIPNAME DAP -irlen 4 -ircapture 0x1 -irmask 0xf \ jtag newtap $_CHIPNAME SDMA -irlen 4 -ircapture 0x0 -irmask 0xf # SJC -if { [info exists SJC_TAPID ] } { +if { [info exists SJC_TAPID] } { set _SJC_TAPID SJC_TAPID } else { set _SJC_TAPID 0x0190d01d @@ -29,7 +29,7 @@ if { [info exists SJC_TAPID ] } { jtag newtap $_CHIPNAME SJC -irlen 5 -ircapture 0x1 -irmask 0x1f \ -expected-id $_SJC_TAPID -ignore-version -# GDB target: Cortex-A8, using DAP +# GDB target: Cortex-A8, using DAP set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.DAP diff --git a/tcl/target/is5114.cfg b/tcl/target/is5114.cfg index 56b9b65..defd43c 100644 --- a/tcl/target/is5114.cfg +++ b/tcl/target/is5114.cfg @@ -3,19 +3,19 @@ # ATMEL sold his product line to Insilica... if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME is5114 + set _CHIPNAME is5114 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { # this defaults to a little endian - set _ENDIAN little + set _ENDIAN little } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { # Force an error until we get a good number. @@ -36,7 +36,7 @@ jtag newtap $_CHIPNAME unknown2 -irlen 5 -ircapture 1 -irmask 1 #arm946e-s and set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e +target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e $_TARGETNAME configure -event reset-start { jtag_rclk 16 } $_TARGETNAME configure -event reset-init { diff --git a/tcl/target/ixp42x.cfg b/tcl/target/ixp42x.cfg index 6e5857a..9dd9f51 100644 --- a/tcl/target/ixp42x.cfg +++ b/tcl/target/ixp42x.cfg @@ -1,19 +1,19 @@ #xscale ixp42x CPU if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME ixp42x + set _CHIPNAME ixp42x } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { # this defaults to a bigendian - set _ENDIAN big + set _ENDIAN big } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x19274013 @@ -36,21 +36,21 @@ global IXP425_SDRAM_IR_MODE_SET_CAS3_CMD set IXP425_SDRAM_IR_MODE_SET_CAS2_CMD 0x0000 set IXP425_SDRAM_IR_MODE_SET_CAS3_CMD 0x0001 -global IXP42x_SDRAM_CL3 -global IXP42x_SDRAM_CL2 +global IXP42x_SDRAM_CL3 +global IXP42x_SDRAM_CL2 set IXP42x_SDRAM_CL3 0x0008 set IXP42x_SDRAM_CL2 0x0000 -global IXP42x_SDRAM_8MB_2Mx32_1BANK -global IXP42x_SDRAM_16MB_2Mx32_2BANK -global IXP42x_SDRAM_16MB_4Mx16_1BANK -global IXP42x_SDRAM_32MB_4Mx16_2BANK -global IXP42x_SDRAM_32MB_8Mx16_1BANK -global IXP42x_SDRAM_64MB_8Mx16_2BANK -global IXP42x_SDRAM_64MB_16Mx16_1BANK -global IXP42x_SDRAM_128MB_16Mx16_2BANK -global IXP42x_SDRAM_128MB_32Mx16_1BANK -global IXP42x_SDRAM_256MB_32Mx16_2BANK +global IXP42x_SDRAM_8MB_2Mx32_1BANK +global IXP42x_SDRAM_16MB_2Mx32_2BANK +global IXP42x_SDRAM_16MB_4Mx16_1BANK +global IXP42x_SDRAM_32MB_4Mx16_2BANK +global IXP42x_SDRAM_32MB_8Mx16_1BANK +global IXP42x_SDRAM_64MB_8Mx16_2BANK +global IXP42x_SDRAM_64MB_16Mx16_1BANK +global IXP42x_SDRAM_128MB_16Mx16_2BANK +global IXP42x_SDRAM_128MB_32Mx16_1BANK +global IXP42x_SDRAM_256MB_32Mx16_2BANK set IXP42x_SDRAM_8MB_2Mx32_1BANK 0x0030 set IXP42x_SDRAM_16MB_2Mx32_2BANK 0x0031 @@ -71,13 +71,13 @@ set IXP42x_SDRAM_256MB_32Mx16_2BANK 0x0015 proc ixp42x_init_sdram { SDRAM_CFG REFRESH CASLAT } { switch $CASLAT { - 2 { - set SDRAM_CFG [expr $SDRAM_CFG | $::IXP42x_SDRAM_CL2 ] - set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS2_CMD + 2 { + set SDRAM_CFG [expr $SDRAM_CFG | $::IXP42x_SDRAM_CL2 ] + set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS2_CMD } 3 { - set SDRAM_CFG [expr $SDRAM_CFG | $::IXP42x_SDRAM_CL3 ] - set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS3_CMD + set SDRAM_CFG [expr $SDRAM_CFG | $::IXP42x_SDRAM_CL3 ] + set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS3_CMD } default { error [format "unsupported cas latency \"%s\" " $CASLAT] } } diff --git a/tcl/target/k40.cfg b/tcl/target/k40.cfg index 9984bfc..26b952b 100644 --- a/tcl/target/k40.cfg +++ b/tcl/target/k40.cfg @@ -19,7 +19,7 @@ if { [info exists ENDIAN] } { set _ENDIAN little } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x4ba00477 diff --git a/tcl/target/lpc1768.cfg b/tcl/target/lpc1768.cfg index 2059aed..6478b2c 100644 --- a/tcl/target/lpc1768.cfg +++ b/tcl/target/lpc1768.cfg @@ -5,9 +5,9 @@ source [find target/swj-dp.tcl] if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME lpc1768 + set _CHIPNAME lpc1768 } # After reset the chip is clocked by the ~4MHz internal RC oscillator. @@ -17,12 +17,12 @@ if { [info exists CHIPNAME] } { # (The ROM code doing those updates cares about core clock speed...) # # CCLK is the core clock frequency in KHz -if { [info exists CCLK ] } { +if { [info exists CCLK] } { set _CCLK $CCLK } else { set _CCLK 4000 } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x4ba00477 diff --git a/tcl/target/lpc2900.cfg b/tcl/target/lpc2900.cfg index b258086..6b174f8 100644 --- a/tcl/target/lpc2900.cfg +++ b/tcl/target/lpc2900.cfg @@ -1,25 +1,25 @@ if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME lpc2900 + set _CHIPNAME lpc2900 } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x0596802B } -if { [info exists HAS_ETB ] } { +if { [info exists HAS_ETB] } { } else { # Set default (no ETB). # Show a warning, because this should have been configured explicitely. set HAS_ETB 0 - # TODO warning? + # TODO: warning? } -if { [info exists ETBTAPID ] } { +if { [info exists ETBTAPID] } { set _ETBTAPID $ETBTAPID } else { set _ETBTAPID 0x1B900F0F @@ -60,7 +60,7 @@ arm7_9 dbgrq enable arm7_9 dcc_downloads enable # Flash bank configuration: -# Flash: flash bank lpc2900 0 0 0 0 <target#> <flash clock (CLK_SYS_FMC) in kHz> +# Flash: flash bank lpc2900 0 0 0 0 <target#> <flash clock (CLK_SYS_FMC) in kHz> # Flash base address, total flash size, and number of sectors are all configured automatically. set _FLASHNAME $_CHIPNAME.flash flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME $FLASH_CLOCK diff --git a/tcl/target/lpc2xxx.cfg b/tcl/target/lpc2xxx.cfg index e9e8e6d..b946d44 100644 --- a/tcl/target/lpc2xxx.cfg +++ b/tcl/target/lpc2xxx.cfg @@ -11,24 +11,24 @@ proc setup_lpc2xxx {chip_name cputapids flash_size flash_variant workarea_size core_freq_khz adapter_freq_khz} { reset_config trst_and_srst - + # reset delays adapter_nsrst_delay 100 jtag_ntrst_delay 100 - + adapter_khz $adapter_freq_khz - + foreach i $cputapids { append expected_ids "-expected-id " $i " " } - + eval "jtag newtap $chip_name cpu -irlen 4 -ircapture 0x1 -irmask 0xf $expected_ids" - + set _TARGETNAME $chip_name.cpu target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME - + $_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size $workarea_size -work-area-backup 0 - + if { $flash_size > 0 } { # flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum] set _FLASHNAME $chip_name.flash diff --git a/tcl/target/lpc3131.cfg b/tcl/target/lpc3131.cfg index 560555b..702b406 100644 --- a/tcl/target/lpc3131.cfg +++ b/tcl/target/lpc3131.cfg @@ -3,19 +3,19 @@ ###################################### if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME lpc3131 + set _CHIPNAME lpc3131 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } # ARM926EJS core -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x07926f0f @@ -24,7 +24,7 @@ if { [info exists CPUTAPID ] } { # Scan Tap # Wired to seperate STDO pin on the lpc3131, externally muxed to TDO on ea3131 module # JTAGSEL pin must be 0 to activate, which reassigns arm tdo to a pass through. -if { [info exists SJCTAPID ] } { +if { [info exists SJCTAPID] } { set _SJCTAPID $SJCTAPID } else { set _SJCTAPID 0x1541E02B diff --git a/tcl/target/lpc3250.cfg b/tcl/target/lpc3250.cfg index 02340ff..14bb0f6 100644 --- a/tcl/target/lpc3250.cfg +++ b/tcl/target/lpc3250.cfg @@ -2,30 +2,30 @@ # if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME lpc3250 + set _CHIPNAME lpc3250 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x17900f0f } -if { [info exists CPUTAPID_REV_A0 ] } { +if { [info exists CPUTAPID_REV_A0] } { set _CPUTAPID_REV_A0 $CPUTAPID_REV_A0 } else { set _CPUTAPID_REV_A0 0x17926f0f } -if { [info exists SJCTAPID ] } { +if { [info exists SJCTAPID] } { set _SJCTAPID $SJCTAPID } else { set _SJCTAPID 0x1b900f0f diff --git a/tcl/target/mc13224v.cfg b/tcl/target/mc13224v.cfg index 33351ca..8037125 100644 --- a/tcl/target/mc13224v.cfg +++ b/tcl/target/mc13224v.cfg @@ -3,19 +3,19 @@ source [find cpu/arm/arm7tdmi.tcl] source [find memory.tcl] source [find mmr_helpers.tcl] -set CHIP_MAKER freescale -set CHIP_FAMILY mc1322x -set CHIP_NAME mc13224 -set N_RAM 1 -set RAM(0,BASE) 0x00400000 -set RAM(0,LEN) 0x18000 -set RAM(0,HUMAN) "internal SRAM" +set CHIP_MAKER freescale +set CHIP_FAMILY mc1322x +set CHIP_NAME mc13224 +set N_RAM 1 +set RAM(0,BASE) 0x00400000 +set RAM(0,LEN) 0x18000 +set RAM(0,HUMAN) "internal SRAM" set RAM(0,TYPE) "ram" set RAM(0,RWX) $RWX_RWX set RAM(0,ACCESS_WIDTH) $ACCESS_WIDTH_ANY # I AM LAZY... I create 1 region for all MMRs. -set N_MMREGS 1 +set N_MMREGS 1 set MMREGS(0,CHIPSELECT) -1 set MMREGS(0,BASE) 0x80000000 set MMREGS(0,LEN) 0x00030000 diff --git a/tcl/target/nuc910.cfg b/tcl/target/nuc910.cfg index 7fe91fe..29cd29f 100644 --- a/tcl/target/nuc910.cfg +++ b/tcl/target/nuc910.cfg @@ -3,18 +3,18 @@ # if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME nuc910 + set _CHIPNAME nuc910 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { # set useful default diff --git a/tcl/target/omap2420.cfg b/tcl/target/omap2420.cfg index 86b0a80..7968ad1 100644 --- a/tcl/target/omap2420.cfg +++ b/tcl/target/omap2420.cfg @@ -3,22 +3,22 @@ # as seen in Nokia N8x0 tablets if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME omap2420 + set _CHIPNAME omap2420 } # NOTE: likes slowish clock on reset (1.5 MBit/s or less) or use RCLK reset_config srst_nogate -# Subsidiary TAP: ARM7TDMIr4 plus imaging ... must add via ICEpick (addr 6). +# Subsidiary TAP: ARM7TDMIr4 plus imaging ... must add via ICEpick (addr 6). jtag newtap $_CHIPNAME iva -irlen 4 -disable # Subsidiary TAP: C55x DSP ... must add via ICEpick (addr 2). jtag newtap $_CHIPNAME dsp -irlen 38 -disable # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer -if { [info exists ETB_TAPID ] } { +if { [info exists ETB_TAPID] } { set _ETB_TAPID $ETB_TAPID } else { set _ETB_TAPID 0x2b900f0f @@ -26,7 +26,7 @@ if { [info exists ETB_TAPID ] } { jtag newtap $_CHIPNAME etb -irlen 4 -expected-id $_ETB_TAPID # Subsidiary TAP: ARM1136jf-s with scan chains for ARM Debug, EmbeddedICE-RT, ETM. -if { [info exists CPU_TAPID ] } { +if { [info exists CPU_TAPID] } { set _CPU_TAPID $CPU_TAPID } else { set _CPU_TAPID 0x07b3602f @@ -34,18 +34,18 @@ if { [info exists CPU_TAPID ] } { jtag newtap $_CHIPNAME arm -irlen 5 -expected-id $_CPU_TAPID # Primary TAP: ICEpick-B (JTAG route controller) and boundary scan -if { [info exists JRC_TAPID ] } { +if { [info exists JRC_TAPID] } { set _JRC_TAPID $JRC_TAPID } else { set _JRC_TAPID 0x01ce4801 } jtag newtap $_CHIPNAME jrc -irlen 2 -expected-id $_JRC_TAPID -# GDB target: the ARM. +# GDB target: the ARM. set _TARGETNAME $_CHIPNAME.arm target create $_TARGETNAME arm11 -chain-position $_TARGETNAME -# scratch: framebuffer, may be initially unavailable in some chips +# scratch: framebuffer, may be initially unavailable in some chips $_TARGETNAME configure -work-area-phys 0x40210000 $_TARGETNAME configure -work-area-size 0x00081000 $_TARGETNAME configure -work-area-backup 0 diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg index ba130a9..018363a 100644 --- a/tcl/target/omap3530.cfg +++ b/tcl/target/omap3530.cfg @@ -1,11 +1,11 @@ # TI OMAP3530 -# http://focus.ti.com/docs/prod/folders/print/omap3530.html +# http://focus.ti.com/docs/prod/folders/print/omap3530.html # Other OMAP3 chips remove DSP and/or the OpenGL support if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME omap3530 + set _CHIPNAME omap3530 } # ICEpick-C ... used to route Cortex, DSP, and more not shown here @@ -15,7 +15,7 @@ source [find target/icepick.cfg] jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable # Subsidiary TAP: CoreSight Debug Access Port (DAP) -if { [info exists DAP_TAPID ] } { +if { [info exists DAP_TAPID] } { set _DAP_TAPID $DAP_TAPID } else { set _DAP_TAPID 0x0b6d602f @@ -26,7 +26,7 @@ jtag configure $_CHIPNAME.dap -event tap-enable \ "icepick_c_tapenable $_CHIPNAME.jrc 3" # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan -if { [info exists JRC_TAPID ] } { +if { [info exists JRC_TAPID] } { set _JRC_TAPID $JRC_TAPID } else { set _JRC_TAPID 0x0b7ae02f @@ -34,7 +34,7 @@ if { [info exists JRC_TAPID ] } { jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \ -expected-id $_JRC_TAPID -# GDB target: Cortex-A8, using DAP +# GDB target: Cortex-A8, using DAP set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap diff --git a/tcl/target/omap4430.cfg b/tcl/target/omap4430.cfg index fc3db5d..f16d748 100644 --- a/tcl/target/omap4430.cfg +++ b/tcl/target/omap4430.cfg @@ -16,7 +16,7 @@ source [find target/icepick.cfg] # # A9 DAP # -if { [info exists DAP_TAPID ] } { +if { [info exists DAP_TAPID] } { set _DAP_TAPID $DAP_TAPID } else { set _DAP_TAPID 0x3BA00477 @@ -31,7 +31,7 @@ jtag configure $_CHIPNAME.dap -event tap-enable \ # # M3 DAPs, one per core # -if { [info exists M3_DAP_TAPID ] } { +if { [info exists M3_DAP_TAPID] } { set _M3_DAP_TAPID $M3_DAP_TAPID } else { set _M3_DAP_TAPID 0x4BA00477 @@ -51,7 +51,7 @@ jtag configure $_CHIPNAME.m30_dap -event tap-enable \ # # ICEpick-D JRC (JTAG route controller) # -if { [info exists JRC_TAPID ] } { +if { [info exists JRC_TAPID] } { set _JRC_TAPID $JRC_TAPID } else { set _JRC_TAPID 0x3b95c02f @@ -59,7 +59,7 @@ if { [info exists JRC_TAPID ] } { } # PandaBoard REV EA1 (PEAP platforms) -if { [info exists JRC_TAPID2 ] } { +if { [info exists JRC_TAPID2] } { set _JRC_TAPID2 $JRC_TAPID2 } else { set _JRC_TAPID2 0x1b85202f @@ -68,7 +68,7 @@ if { [info exists JRC_TAPID2 ] } { jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \ - -expected-id $_JRC_TAPID -expected-id $_JRC_TAPID2 + -expected-id $_JRC_TAPID -expected-id $_JRC_TAPID2 # Required by ICEpick to power-up the debug domain jtag configure $_CHIPNAME.jrc -event post-reset "runtest 200" diff --git a/tcl/target/omap5912.cfg b/tcl/target/omap5912.cfg index ed64f52..c4ff40e 100644 --- a/tcl/target/omap5912.cfg +++ b/tcl/target/omap5912.cfg @@ -2,12 +2,12 @@ # http://focus.ti.com/docs/prod/folders/print/omap5912.html if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME omap5912 + set _CHIPNAME omap5912 } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { # NOTE: validated with XOMAP5912 part @@ -16,7 +16,7 @@ if { [info exists CPUTAPID ] } { adapter_nsrst_delay 100 -# NOTE: presumes irlen 38 is the C55x DSP, matching BSDL for +# NOTE: presumes irlen 38 is the C55x DSP, matching BSDL for # its standalone siblings (like TMS320VC5502) of the same era #jtag scan chain diff --git a/tcl/target/omapl138.cfg b/tcl/target/omapl138.cfg index 6e06a19..d3e472c 100644 --- a/tcl/target/omapl138.cfg +++ b/tcl/target/omapl138.cfg @@ -1,16 +1,16 @@ # -# Texas Instruments DaVinci family: OMAPL138 +# Texas Instruments DaVinci family: OMAPL138 # if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME omapl138 + set _CHIPNAME omapl138 } source [find target/icepick.cfg] # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer -if { [info exists ETB_TAPID ] } { +if { [info exists ETB_TAPID] } { set _ETB_TAPID $ETB_TAPID } else { set _ETB_TAPID 0x2b900f0f @@ -20,7 +20,7 @@ jtag configure $_CHIPNAME.etb -event tap-enable \ "icepick_c_tapenable $_CHIPNAME.jrc 3" # Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM. -if { [info exists CPU_TAPID ] } { +if { [info exists CPU_TAPID] } { set _CPU_TAPID $CPU_TAPID } else { set _CPU_TAPID 0x07926001 @@ -30,7 +30,7 @@ jtag configure $_CHIPNAME.arm -event tap-enable \ "icepick_c_tapenable $_CHIPNAME.jrc 2" # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan -if { [info exists JRC_TAPID ] } { +if { [info exists JRC_TAPID] } { set _JRC_TAPID $JRC_TAPID } else { set _JRC_TAPID 0x0b7d102f diff --git a/tcl/target/pic32mx.cfg b/tcl/target/pic32mx.cfg index 0b3522e..5e64cb8 100644 --- a/tcl/target/pic32mx.cfg +++ b/tcl/target/pic32mx.cfg @@ -1,17 +1,16 @@ - if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME pic32mx + set _CHIPNAME pic32mx } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x30938053 @@ -19,12 +18,11 @@ if { [info exists CPUTAPID ] } { # default working area is 16384 if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE + set _WORKAREASIZE $WORKAREASIZE } else { - set _WORKAREASIZE 0x4000 + set _WORKAREASIZE 0x4000 } - adapter_nsrst_delay 100 jtag_ntrst_delay 100 diff --git a/tcl/target/pxa255.cfg b/tcl/target/pxa255.cfg index 5b745f8..3862425 100644 --- a/tcl/target/pxa255.cfg +++ b/tcl/target/pxa255.cfg @@ -1,19 +1,19 @@ # PXA255 chip ... originally from Intel, PXA line was sold to Marvell. -# This chip is now at end-of-life. Final orders have been taken. +# This chip is now at end-of-life. Final orders have been taken. if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME pxa255 + set _CHIPNAME pxa255 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x69264013 diff --git a/tcl/target/pxa270.cfg b/tcl/target/pxa270.cfg index f5d2c85..62cb4f4 100644 --- a/tcl/target/pxa270.cfg +++ b/tcl/target/pxa270.cfg @@ -1,33 +1,33 @@ #Marvell/Intel PXA270 Script if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME pxa270 + set _CHIPNAME pxa270 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } #IDs for pxa270. Are there more? -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { # set useful default set _CPUTAPID 0x49265013 } -if { [info exists CPUTAPID2 ] } { +if { [info exists CPUTAPID2] } { set _CPUTAPID2 $CPUTAPID2 } else { # set useful default set _CPUTAPID2 0x79265013 } -if { [info exists CPUTAPID3 ] } { +if { [info exists CPUTAPID3] } { set _CPUTAPID2 $CPUTAPID3 } else { # set useful default diff --git a/tcl/target/pxa3xx.cfg b/tcl/target/pxa3xx.cfg index 62c325b..832152b 100644 --- a/tcl/target/pxa3xx.cfg +++ b/tcl/target/pxa3xx.cfg @@ -1,59 +1,59 @@ # Marvell PXA3xx if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME pxa3xx + set _CHIPNAME pxa3xx } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } # IDs for all currently known PXA3xx chips -if { [info exists CPUTAPID_PXA30X_A0 ] } { +if { [info exists CPUTAPID_PXA30X_A0] } { set _CPUTAPID_PXA30X_A0 $CPUTAPID_PXA30X_A0 } else { set _CPUTAPID_PXA30X_A0 0x0E648013 } -if { [info exists CPUTAPID_PXA30X_A1 ] } { +if { [info exists CPUTAPID_PXA30X_A1] } { set _CPUTAPID_PXA30X_A1 $CPUTAPID_PXA30X_A1 } else { set _CPUTAPID_PXA30X_A1 0x1E648013 } -if { [info exists CPUTAPID_PXA31X_A0 ] } { +if { [info exists CPUTAPID_PXA31X_A0] } { set _CPUTAPID_PXA31X_A0 $CPUTAPID_PXA31X_A0 } else { set _CPUTAPID_PXA31X_A0 0x0E649013 } -if { [info exists CPUTAPID_PXA31X_A1 ] } { +if { [info exists CPUTAPID_PXA31X_A1] } { set _CPUTAPID_PXA31X_A1 $CPUTAPID_PXA31X_A1 } else { set _CPUTAPID_PXA31X_A1 0x1E649013 } -if { [info exists CPUTAPID_PXA31X_A2 ] } { +if { [info exists CPUTAPID_PXA31X_A2] } { set _CPUTAPID_PXA31X_A2 $CPUTAPID_PXA31X_A2 } else { set _CPUTAPID_PXA31X_A2 0x2E649013 } -if { [info exists CPUTAPID_PXA31X_B0 ] } { +if { [info exists CPUTAPID_PXA31X_B0] } { set _CPUTAPID_PXA31X_B0 $CPUTAPID_PXA31X_B0 } else { set _CPUTAPID_PXA31X_B0 0x3E649013 } -if { [info exists CPUTAPID_PXA32X_B1 ] } { +if { [info exists CPUTAPID_PXA32X_B1] } { set _CPUTAPID_PXA32X_B1 $CPUTAPID_PXA32X_B1 } else { set _CPUTAPID_PXA32X_B1 0x5E642013 } -if { [info exists CPUTAPID_PXA32X_B2 ] } { +if { [info exists CPUTAPID_PXA32X_B2] } { set _CPUTAPID_PXA32X_B2 $CPUTAPID_PXA32X_B2 } else { set _CPUTAPID_PXA32X_B2 0x6E642013 } -if { [info exists CPUTAPID_PXA32X_C0 ] } { +if { [info exists CPUTAPID_PXA32X_C0] } { set _CPUTAPID_PXA32X_C0 $CPUTAPID_PXA32X_C0 } else { set _CPUTAPID_PXA32X_C0 0x7E642013 diff --git a/tcl/target/samsung_s3c2410.cfg b/tcl/target/samsung_s3c2410.cfg index 73d3b50..ae7a138 100644 --- a/tcl/target/samsung_s3c2410.cfg +++ b/tcl/target/samsung_s3c2410.cfg @@ -1,23 +1,23 @@ # Found on the 'TinCanTools' Hammer board. if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME s3c2410 + set _CHIPNAME s3c2410 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { # This config file was defaulting to big endian.. - set _ENDIAN little + set _ENDIAN little } if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID + set _CPUTAPID $CPUTAPID } else { # Force an error until we get a good number. - set _CPUTAPID 0xffffffff + set _CPUTAPID 0xffffffff } #use combined on interfaces or targets that cannot set TRST/SRST separately diff --git a/tcl/target/samsung_s3c2440.cfg b/tcl/target/samsung_s3c2440.cfg index 9cd27d1..9d66337 100644 --- a/tcl/target/samsung_s3c2440.cfg +++ b/tcl/target/samsung_s3c2440.cfg @@ -4,19 +4,19 @@ # Info: JTAG tap: s3c2440.cpu tap/device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0) if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME s3c2440 + set _CHIPNAME s3c2440 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { # this defaults to a bigendian - set _ENDIAN little + set _ENDIAN little } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x0032409d diff --git a/tcl/target/samsung_s3c2450.cfg b/tcl/target/samsung_s3c2450.cfg index 164fe16..89a2ea8 100644 --- a/tcl/target/samsung_s3c2450.cfg +++ b/tcl/target/samsung_s3c2450.cfg @@ -14,19 +14,19 @@ # adapter_khz 1 if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME s3c2450 + set _CHIPNAME s3c2450 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { # this defaults to a bigendian - set _ENDIAN little + set _ENDIAN little } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x07926f0f diff --git a/tcl/target/samsung_s3c4510.cfg b/tcl/target/samsung_s3c4510.cfg index f1cbff7..461d047 100644 --- a/tcl/target/samsung_s3c4510.cfg +++ b/tcl/target/samsung_s3c4510.cfg @@ -1,19 +1,18 @@ - if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME s3c4510 + set _CHIPNAME s3c4510 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } # This appears to be a "Version 1" arm7tdmi. -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x1f0f0f0f diff --git a/tcl/target/samsung_s3c6410.cfg b/tcl/target/samsung_s3c6410.cfg index eb95242..07fd425 100644 --- a/tcl/target/samsung_s3c6410.cfg +++ b/tcl/target/samsung_s3c6410.cfg @@ -7,26 +7,26 @@ # [and I do not believe it to be accurate, hence the 0xffffffff below] if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME s3c6410 + set _CHIPNAME s3c6410 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { # this defaults to a bigendian - set _ENDIAN little + set _ENDIAN little } # trace buffer -if { [info exists ETBTAPID ] } { +if { [info exists ETBTAPID] } { set _ETBTAPID $ETBTAPID } else { set _ETBTAPID 0x2b900f0f } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x07b76f0f @@ -35,10 +35,10 @@ if { [info exists CPUTAPID ] } { #jtag scan chain jtag newtap $_CHIPNAME etb -irlen 4 -expected-id $_ETBTAPID -jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID +jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm1176 +target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm1176 adapter_nsrst_delay 500 jtag_ntrst_delay 500 diff --git a/tcl/target/sharp_lh79532.cfg b/tcl/target/sharp_lh79532.cfg index ed9feee..6f2cf22 100644 --- a/tcl/target/sharp_lh79532.cfg +++ b/tcl/target/sharp_lh79532.cfg @@ -1,18 +1,18 @@ reset_config srst_only srst_pulls_trst if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME lh79532 + set _CHIPNAME lh79532 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { # sharp changed the number! diff --git a/tcl/target/smp8634.cfg b/tcl/target/smp8634.cfg index dc9bf0b..5207a44 100644 --- a/tcl/target/smp8634.cfg +++ b/tcl/target/smp8634.cfg @@ -1,18 +1,18 @@ # script for Sigma Designs SMP8634 (eventually even SMP8635) if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME smp8634 + set _CHIPNAME smp8634 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x08630001 @@ -25,7 +25,7 @@ reset_config trst_and_srst separate # jtag scan chain # format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1 +jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1 set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME mips_m4k -endian $_ENDIAN -variant diff --git a/tcl/target/spear3xx.cfg b/tcl/target/spear3xx.cfg index ef289e3..a86a3c4 100644 --- a/tcl/target/spear3xx.cfg +++ b/tcl/target/spear3xx.cfg @@ -19,7 +19,7 @@ if { [info exists ENDIAN] } { set _ENDIAN little } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x07926041 diff --git a/tcl/target/stellaris.cfg b/tcl/target/stellaris.cfg index 3ab5c0b..a272e66 100644 --- a/tcl/target/stellaris.cfg +++ b/tcl/target/stellaris.cfg @@ -6,7 +6,7 @@ global _DEVICECLASS -if { [info exists DEVICECLASS ] } { +if { [info exists DEVICECLASS] } { set _DEVICECLASS $DEVICECLASS } else { set _DEVICECLASS 0xff @@ -20,9 +20,9 @@ source [find target/swj-dp.tcl] # are usable only for ISP style initial flash programming. if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME lm3s + set _CHIPNAME lm3s } # CPU TAP ID 0x1ba00477 for early Sandstorm parts @@ -31,7 +31,7 @@ if { [info exists CHIPNAME] } { # CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest) # ... we'll ignore the JTAG version field, rather than list every # chip revision that turns up. -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x0ba00477 @@ -43,7 +43,7 @@ if { [info exists CPUTAPID ] } { swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf \ -expected-id $_CPUTAPID -ignore-version -if { [info exists WORKAREASIZE ] } { +if { [info exists WORKAREASIZE] } { set _WORKAREASIZE $WORKAREASIZE } else { # default to 8K working area @@ -55,7 +55,7 @@ target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu # 8K working area at base of ram, not backed up # -# NOTE: you may need or want to reconfigure the work area; +# NOTE: you may need or want to reconfigure the work area; # some parts have just 6K, and you may want to use other # addresses (at end of mem not beginning) or back it up. $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE @@ -63,7 +63,7 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE # JTAG speed ... slow enough to work with a 12 MHz RC oscillator; # LM3S parts don't support RTCK # -# NOTE: this may be increased by a reset-init handler, after it +# NOTE: this may be increased by a reset-init handler, after it # configures and enables the PLL. Or you might need to decrease # this, if you're using a slower clock. adapter_khz 500 diff --git a/tcl/target/stm32f1x.cfg b/tcl/target/stm32f1x.cfg index 25a6059..2390f28 100644 --- a/tcl/target/stm32f1x.cfg +++ b/tcl/target/stm32f1x.cfg @@ -1,23 +1,23 @@ # script for stm32 if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME stm32 + set _CHIPNAME stm32 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } # Work-area is a space in RAM used for flash programming # By default use 16kB if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE + set _WORKAREASIZE $WORKAREASIZE } else { - set _WORKAREASIZE 0x4000 + set _WORKAREASIZE 0x4000 } # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz @@ -27,7 +27,7 @@ adapter_nsrst_delay 100 jtag_ntrst_delay 100 #jtag scan chain -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { # See STM Document RM0008 @@ -36,7 +36,7 @@ if { [info exists CPUTAPID ] } { } jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID -if { [info exists BSTAPID ] } { +if { [info exists BSTAPID] } { # FIXME this never gets used to override defaults... set _BSTAPID $BSTAPID } else { diff --git a/tcl/target/stm32f2x.cfg b/tcl/target/stm32f2x.cfg index b8de384..a47b115 100644 --- a/tcl/target/stm32f2x.cfg +++ b/tcl/target/stm32f2x.cfg @@ -1,23 +1,23 @@ # script for stm32f2xxx if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME stm32f2xxx + set _CHIPNAME stm32f2xxx } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } # Work-area is a space in RAM used for flash programming # By default use 64kB if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE + set _WORKAREASIZE $WORKAREASIZE } else { - set _WORKAREASIZE 0x10000 + set _WORKAREASIZE 0x10000 } # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz @@ -32,7 +32,7 @@ jtag_nsrst_delay 100 jtag_ntrst_delay 100 #jtag scan chain -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { # See STM Document RM0033 @@ -41,7 +41,7 @@ if { [info exists CPUTAPID ] } { } jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID -if { [info exists BSTAPID ] } { +if { [info exists BSTAPID] } { set _BSTAPID $BSTAPID } else { # See STM Document RM0033 diff --git a/tcl/target/stm32l.cfg b/tcl/target/stm32l.cfg index 5c3d368..940a4e7 100644 --- a/tcl/target/stm32l.cfg +++ b/tcl/target/stm32l.cfg @@ -1,23 +1,23 @@ # script for stm32l if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME stm32l + set _CHIPNAME stm32l } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } # Work-area is a space in RAM used for flash programming # By default use 14kB if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE + set _WORKAREASIZE $WORKAREASIZE } else { - set _WORKAREASIZE 0x3800 + set _WORKAREASIZE 0x3800 } # JTAG speed should be <= F_CPU/6. @@ -28,7 +28,7 @@ adapter_nsrst_delay 100 jtag_ntrst_delay 100 #jtag scan chain -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { # See STM Document RM0038 @@ -37,7 +37,7 @@ if { [info exists CPUTAPID ] } { } jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID -if { [info exists BSTAPID ] } { +if { [info exists BSTAPID] } { # FIXME this never gets used to override defaults... set _BSTAPID $BSTAPID } else { diff --git a/tcl/target/str710.cfg b/tcl/target/str710.cfg index 0f61d44..0c458c0 100644 --- a/tcl/target/str710.cfg +++ b/tcl/target/str710.cfg @@ -2,21 +2,21 @@ adapter_khz 10 if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME str710 + set _CHIPNAME str710 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID + set _CPUTAPID $CPUTAPID } else { - set _CPUTAPID 0x3f0f0f0f + set _CPUTAPID 0x3f0f0f0f } #use combined on interfaces or targets that can't set TRST/SRST separately diff --git a/tcl/target/str730.cfg b/tcl/target/str730.cfg index a1491ff..cf125ab 100644 --- a/tcl/target/str730.cfg +++ b/tcl/target/str730.cfg @@ -3,21 +3,21 @@ adapter_khz 3000 if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME str730 + set _CHIPNAME str730 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID + set _CPUTAPID $CPUTAPID } else { - set _CPUTAPID 0x3f0f0f0f + set _CPUTAPID 0x3f0f0f0f } #use combined on interfaces or targets that can't set TRST/SRST separately diff --git a/tcl/target/str750.cfg b/tcl/target/str750.cfg index 686aede..e916727 100644 --- a/tcl/target/str750.cfg +++ b/tcl/target/str750.cfg @@ -1,21 +1,21 @@ #STR750 CPU if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME str750 + set _CHIPNAME str750 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID + set _CPUTAPID $CPUTAPID } else { - set _CPUTAPID 0x4f1f0041 + set _CPUTAPID 0x4f1f0041 } # jtag speed @@ -35,7 +35,7 @@ jtag_ntrst_delay 500 set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME arm7tdmi -endian little -chain-position 0 -variant arm7tdmi -$_TARGETNAME configure -event reset-start { adapter_khz 10 } +$_TARGETNAME configure -event reset-start { adapter_khz 10 } $_TARGETNAME configure -event reset-init { adapter_khz 3000 diff --git a/tcl/target/str912.cfg b/tcl/target/str912.cfg index 9b0a708..57bf8b6 100644 --- a/tcl/target/str912.cfg +++ b/tcl/target/str912.cfg @@ -1,15 +1,15 @@ # script for str9 if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME str912 + set _CHIPNAME str912 } if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN + set _ENDIAN $ENDIAN } else { - set _ENDIAN little + set _ENDIAN little } # jtag speed. We need to stick to 16kHz until we've finished reset. @@ -21,27 +21,27 @@ jtag_ntrst_delay 100 #use combined on interfaces or targets that can't set TRST/SRST separately reset_config trst_and_srst -if { [info exists FLASHTAPID ] } { +if { [info exists FLASHTAPID] } { set _FLASHTAPID $FLASHTAPID } else { set _FLASHTAPID 0x04570041 } jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x25966041 } -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID -if { [info exists BSTAPID ] } { +if { [info exists BSTAPID] } { set _BSTAPID $BSTAPID } else { set _BSTAPID 0x1457f041 } -jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID +jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e diff --git a/tcl/target/ti_dm355.cfg b/tcl/target/ti_dm355.cfg index 2551c3e..2903e5d 100644 --- a/tcl/target/ti_dm355.cfg +++ b/tcl/target/ti_dm355.cfg @@ -1,10 +1,10 @@ # -# Texas Instruments DaVinci family: TMS320DM355 +# Texas Instruments DaVinci family: TMS320DM355 # if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME dm355 + set _CHIPNAME dm355 } # TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled* @@ -18,12 +18,12 @@ set EMU01 "-disable" source [find target/icepick.cfg] # -# Also note: when running without RTCK before the PLLs are set up, you +# Also note: when running without RTCK before the PLLs are set up, you # may need to slow the JTAG clock down quite a lot (under 2 MHz). # # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer -if { [info exists ETB_TAPID ] } { +if { [info exists ETB_TAPID] } { set _ETB_TAPID $ETB_TAPID } else { set _ETB_TAPID 0x2b900f0f @@ -33,7 +33,7 @@ jtag configure $_CHIPNAME.etb -event tap-enable \ "icepick_c_tapenable $_CHIPNAME.jrc 1" # Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM. -if { [info exists CPU_TAPID ] } { +if { [info exists CPU_TAPID] } { set _CPU_TAPID $CPU_TAPID } else { set _CPU_TAPID 0x07926001 @@ -43,7 +43,7 @@ jtag configure $_CHIPNAME.arm -event tap-enable \ "icepick_c_tapenable $_CHIPNAME.jrc 0" # Primary TAP: ICEpick (JTAG route controller) and boundary scan -if { [info exists JRC_TAPID ] } { +if { [info exists JRC_TAPID] } { set _JRC_TAPID $JRC_TAPID } else { set _JRC_TAPID 0x0b73b02f @@ -81,7 +81,7 @@ dict set dm355 uart2 0x01e06000 source [find target/davinci.cfg] ################ -# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K) +# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K) # and the ETB memory (4K) are other options, while trace is unused. set _TARGETNAME $_CHIPNAME.arm diff --git a/tcl/target/ti_dm365.cfg b/tcl/target/ti_dm365.cfg index e2d29bd..a260278 100644 --- a/tcl/target/ti_dm365.cfg +++ b/tcl/target/ti_dm365.cfg @@ -1,10 +1,10 @@ # -# Texas Instruments DaVinci family: TMS320DM365 +# Texas Instruments DaVinci family: TMS320DM365 # if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME dm365 + set _CHIPNAME dm365 } # TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled* @@ -18,7 +18,7 @@ set EMU01 "-disable" source [find target/icepick.cfg] # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer -if { [info exists ETB_TAPID ] } { +if { [info exists ETB_TAPID] } { set _ETB_TAPID $ETB_TAPID } else { set _ETB_TAPID 0x2b900f0f @@ -28,7 +28,7 @@ jtag configure $_CHIPNAME.etb -event tap-enable \ "icepick_c_tapenable $_CHIPNAME.jrc 1" # Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM. -if { [info exists CPU_TAPID ] } { +if { [info exists CPU_TAPID] } { set _CPU_TAPID $CPU_TAPID } else { set _CPU_TAPID 0x0792602f @@ -38,7 +38,7 @@ jtag configure $_CHIPNAME.arm -event tap-enable \ "icepick_c_tapenable $_CHIPNAME.jrc 0" # Primary TAP: ICEpick (JTAG route controller) and boundary scan -if { [info exists JRC_TAPID ] } { +if { [info exists JRC_TAPID] } { set _JRC_TAPID $JRC_TAPID } else { set _JRC_TAPID 0x0b83e02f @@ -73,7 +73,7 @@ dict set dm365 ddr 0x80000000 source [find target/davinci.cfg] ################ -# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K) +# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K) # and the ETB memory (4K) are other options, while trace is unused. set _TARGETNAME $_CHIPNAME.arm diff --git a/tcl/target/ti_dm6446.cfg b/tcl/target/ti_dm6446.cfg index 4dac3d5..4f10084 100644 --- a/tcl/target/ti_dm6446.cfg +++ b/tcl/target/ti_dm6446.cfg @@ -1,10 +1,10 @@ # -# Texas Instruments DaVinci family: TMS320DM6446 +# Texas Instruments DaVinci family: TMS320DM6446 # if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME dm6446 + set _CHIPNAME dm6446 } # TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled* @@ -28,7 +28,7 @@ jtag configure $_CHIPNAME.dsp -event tap-enable \ "icepick_c_tapenable $_CHIPNAME.jrc 2" # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer -if { [info exists ETB_TAPID ] } { +if { [info exists ETB_TAPID] } { set _ETB_TAPID $ETB_TAPID } else { set _ETB_TAPID 0x2b900f0f @@ -38,7 +38,7 @@ jtag configure $_CHIPNAME.etb -event tap-enable \ "icepick_c_tapenable $_CHIPNAME.jrc 1" # Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM. -if { [info exists CPU_TAPID ] } { +if { [info exists CPU_TAPID] } { set _CPU_TAPID $CPU_TAPID } else { set _CPU_TAPID 0x07926001 @@ -48,7 +48,7 @@ jtag configure $_CHIPNAME.arm -event tap-enable \ "icepick_c_tapenable $_CHIPNAME.jrc 0" # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan -if { [info exists JRC_TAPID ] } { +if { [info exists JRC_TAPID] } { set _JRC_TAPID $JRC_TAPID } else { set _JRC_TAPID 0x0b70002f @@ -59,7 +59,7 @@ jtag configure $_CHIPNAME.jrc -event setup \ "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm" ################ -# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 8K) +# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 8K) # and the ETB memory (4K) are other options, while trace is unused. # Little-endian; use the OpenOCD default. set _TARGETNAME $_CHIPNAME.arm diff --git a/tcl/target/tmpa900.cfg b/tcl/target/tmpa900.cfg index dd5d177..3ba3591 100644 --- a/tcl/target/tmpa900.cfg +++ b/tcl/target/tmpa900.cfg @@ -3,15 +3,15 @@ ###################################### if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME tmpa900 + set _CHIPNAME tmpa900 } # Toshiba TMPA900 series MCUs are always little endian as per datasheet. set _ENDIAN little -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x07926031 diff --git a/tcl/target/tmpa910.cfg b/tcl/target/tmpa910.cfg index 271ca57..5d41c8c 100644 --- a/tcl/target/tmpa910.cfg +++ b/tcl/target/tmpa910.cfg @@ -3,15 +3,15 @@ ###################################### if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME tmpa910 + set _CHIPNAME tmpa910 } # Toshiba TMPA910 series MCUs are always little endian as per datasheet. set _ENDIAN little -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x07926031 diff --git a/tcl/target/u8500.cfg b/tcl/target/u8500.cfg index 073e01f..e136874 100644 --- a/tcl/target/u8500.cfg +++ b/tcl/target/u8500.cfg @@ -15,7 +15,7 @@ proc mmu_on {} { } proc ocd_gdb_restart {target_id} { - global _TARGETNAME_1 + global _TARGETNAME_1 global _SMP targets $_TARGETNAME_1 if { [expr ($_SMP == 1)] } { @@ -29,13 +29,13 @@ proc ocd_gdb_restart {target_id} { } proc smp_reg {} { - global _TARGETNAME_1 - global _TARGETNAME_2 + global _TARGETNAME_1 + global _TARGETNAME_2 targets $_TARGETNAME_1 echo "$_TARGETNAME_1" set pc1 [reg pc] set stck1 [reg sp_svc] - targets $_TARGETNAME_2 + targets $_TARGETNAME_2 echo "$_TARGETNAME_1" set pc2 [reg pc] set stck2 [reg sp_svc] @@ -79,13 +79,13 @@ proc poll_pwrsts { } { set result 1 set i 0 irscan $_CHIPNAME.jrc 0x3a - drscan $_CHIPNAME.jrc 4 0 - set pwrsts [drscan $_CHIPNAME.jrc 16 0] + drscan $_CHIPNAME.jrc 4 0 + set pwrsts [drscan $_CHIPNAME.jrc 16 0] set pwrsts [expr (0x$pwrsts & 0xc)] while {[string equal "4" $pwrsts] && $i<20} { irscan $_CHIPNAME.jrc 0x3a - drscan $_CHIPNAME.jrc 4 0; - set pwrsts [drscan $_CHIPNAME.jrc 16 0] + drscan $_CHIPNAME.jrc 4 0; + set pwrsts [drscan $_CHIPNAME.jrc 16 0] set pwrsts [expr (0x$pwrsts & 0xc)] if {![string equal "4" $pwrsts]} { set result 1 @@ -100,7 +100,7 @@ proc poll_pwrsts { } { } proc halt_ { } { - if {[poll_pwrsts]==1} { + if {[poll_pwrsts]==1} { halt } else { echo "halt failed : target in retention" @@ -117,12 +117,12 @@ proc u8500_tapdisable {chip val} { proc enable_apetap {} { - global _CHIPNAME - global _TARGETNAME_2 + global _CHIPNAME + global _TARGETNAME_2 global _TARGETNAME_1 poll off irscan $_CHIPNAME.jrc 0x3e - drscan $_CHIPNAME.jrc 8 0xcf + drscan $_CHIPNAME.jrc 8 0xcf jtag tapenable $_CHIPNAME.dap irscan $_CHIPNAME.jrc 0x6 drscan $_CHIPNAME.jrc 32 0 @@ -143,26 +143,26 @@ proc enable_apetap {} { tcl_port 5555 telnet_port 4444 gdb_port 3333 - + if { [info exists CHIPNAME] } { -global _CHIPNAME - set _CHIPNAME $CHIPNAME +global _CHIPNAME + set _CHIPNAME $CHIPNAME } else { -global _CHIPNAME - set _CHIPNAME u8500 +global _CHIPNAME + set _CHIPNAME u8500 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { # this defaults to a bigendian - set _ENDIAN little + set _ENDIAN little } # Subsidiary TAP: APE with scan chains for ARM Debug, EmbeddedICE-RT, -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x4ba00477 @@ -175,7 +175,7 @@ jtag configure $_CHIPNAME.dap -event tap-disable \ #CLTAPC TAP JRC equivalent -if { [info exists CLTAPC_ID ] } { +if { [info exists CLTAPC_ID] } { set _CLTAPC_ID $CLTAPC_ID } else { set _CLTAPC_ID 0x22286041 @@ -183,20 +183,20 @@ if { [info exists CLTAPC_ID ] } { jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x6 -irmask 0xf -expected-id $_CLTAPC_ID -ignore-version -if { ![info exists TARGETNAME_1 ] } { -global _TARGETNAME_1 +if { ![info exists TARGETNAME_1] } { +global _TARGETNAME_1 set _TARGETNAME_1 $_CHIPNAME.cpu1 } else { -global _TARGETNAME_1 +global _TARGETNAME_1 set _TARGETNAME_1 $TARGETNAME_1 } -if { [info exists DAP_DBG1] } { +if { [info exists DAP_DBG1] } { set _DAP_DBG1 $DAP_DBG1 } else { set _DAP_DBG1 0x801A8000 } -if { [info exists DAP_DBG2] } { +if { [info exists DAP_DBG2] } { set _DAP_DBG2 $DAP_DBG2 } else { set _DAP_DBG2 0x801AA000 @@ -209,11 +209,11 @@ $_TARGETNAME_1 configure -event gdb-attach { } -if { ![info exists TARGETNAME_2 ] } { -global _TARGETNAME_2 +if { ![info exists TARGETNAME_2] } { +global _TARGETNAME_2 set _TARGETNAME_2 $_CHIPNAME.cpu2 } else { -global _TARGETNAME_2 +global _TARGETNAME_2 set _TARGETNAME_2 $TARGETNAME_2 } |