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author | Spencer Oliver <spen@spen-soft.co.uk> | 2013-02-01 15:34:51 +0000 |
---|---|---|
committer | Freddie Chopin <freddie.chopin@gmail.com> | 2013-04-28 08:55:31 +0000 |
commit | b7d2cdc0d4fc319169c60362708a67e2ff626525 (patch) | |
tree | 1ad1b79b7ff26c47023d30fee6fc7e38266f1ecc /tcl/target/stm32l.cfg | |
parent | 564a5eb5375aa8117ee4fe48899f07490da8ae8a (diff) | |
download | riscv-openocd-b7d2cdc0d4fc319169c60362708a67e2ff626525.zip riscv-openocd-b7d2cdc0d4fc319169c60362708a67e2ff626525.tar.gz riscv-openocd-b7d2cdc0d4fc319169c60362708a67e2ff626525.tar.bz2 |
target: rename cortex_m3 to cortex_m
Rename cortex_m3 target to use a more correct cortex_m name.
This also adds a deprecated_name var so that older scripts issue a warning
to update the target name.
cfg files have also been updated to the new target name.
Change-Id: Ia8429f38e88da677249c5caa560c50f8ce56ea10
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1129
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Diffstat (limited to 'tcl/target/stm32l.cfg')
-rw-r--r-- | tcl/target/stm32l.cfg | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tcl/target/stm32l.cfg b/tcl/target/stm32l.cfg index eea082e..8e6a10e 100644 --- a/tcl/target/stm32l.cfg +++ b/tcl/target/stm32l.cfg @@ -48,7 +48,7 @@ if { [info exists BSTAPID] } { jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME +target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 @@ -59,7 +59,7 @@ flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME # if srst is not fitted use SYSRESETREQ to # perform a soft reset -cortex_m3 reset_config sysresetreq +cortex_m reset_config sysresetreq proc stm32l_enable_HSI {} { # Enable HSI as clock source |