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| author | Tim Newsome <tim@sifive.com> | 2023-11-01 09:07:59 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-11-01 09:07:59 -0700 |
| commit | dc782f6d94ce20268ed3b5e93a5c31112e3bdded (patch) | |
| tree | 4f3b3dbc648900dc181b7d8873c91787e5cd4fdb /doc/openocd.texi | |
| parent | 585f5db11c5328c1cd4f7470b8c5627a993d4dfa (diff) | |
| parent | 2d9c7a7a771cd64d63342bc0a6e3d520dc693bfe (diff) | |
| download | riscv-openocd-dc782f6d94ce20268ed3b5e93a5c31112e3bdded.zip riscv-openocd-dc782f6d94ce20268ed3b5e93a5c31112e3bdded.tar.gz riscv-openocd-dc782f6d94ce20268ed3b5e93a5c31112e3bdded.tar.bz2 | |
Merge pull request #949 from riscv/remove_esp32c_targets_from_doc
Remove mention of esp32c2, esp32c3 from doc
Diffstat (limited to 'doc/openocd.texi')
| -rw-r--r-- | doc/openocd.texi | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index ed6fb79..30bf695 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -4838,8 +4838,6 @@ compact Thumb2 instruction set. Supports also ARMv6-M and ARMv8-M cores @item @code{esirisc} -- this is an EnSilica eSi-RISC core. The current implementation supports eSi-32xx cores. @item @code{esp32} -- this is an Espressif SoC with dual Xtensa cores. -@item @code{esp32c2} -- this is an Espressif SoC with single RISC-V core. -@item @code{esp32c3} -- this is an Espressif SoC with single RISC-V core. @item @code{esp32s2} -- this is an Espressif SoC with single Xtensa core. @item @code{esp32s3} -- this is an Espressif SoC with dual Xtensa cores. @item @code{fa526} -- resembles arm920 (w/o Thumb). |