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| author | Jan Matyas <jan.matyas@codasip.com> | 2023-10-31 16:52:02 +0100 |
|---|---|---|
| committer | Jan Matyas <jan.matyas@codasip.com> | 2023-10-31 16:52:02 +0100 |
| commit | 2d9c7a7a771cd64d63342bc0a6e3d520dc693bfe (patch) | |
| tree | fc7686b67fd49b34ab2d57a2a841dc3984494d9d /doc/openocd.texi | |
| parent | c92149afc386502ef49d3f279d9ed42f648c9ba0 (diff) | |
| download | riscv-openocd-2d9c7a7a771cd64d63342bc0a6e3d520dc693bfe.zip riscv-openocd-2d9c7a7a771cd64d63342bc0a6e3d520dc693bfe.tar.gz riscv-openocd-2d9c7a7a771cd64d63342bc0a6e3d520dc693bfe.tar.bz2 | |
Remove mention of esp32c2, esp32c3 from doc
Targets "esp32c2" and "esp32c3" should not be mentioned in the doc
under "target types" because these are not standalone OpenOCD
targets.
They are merely a set of .cfg files which use the generic
"riscv" target.
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
Diffstat (limited to 'doc/openocd.texi')
| -rw-r--r-- | doc/openocd.texi | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index 7e9eb20..afd8536 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -4838,8 +4838,6 @@ compact Thumb2 instruction set. Supports also ARMv6-M and ARMv8-M cores @item @code{esirisc} -- this is an EnSilica eSi-RISC core. The current implementation supports eSi-32xx cores. @item @code{esp32} -- this is an Espressif SoC with dual Xtensa cores. -@item @code{esp32c2} -- this is an Espressif SoC with single RISC-V core. -@item @code{esp32c3} -- this is an Espressif SoC with single RISC-V core. @item @code{esp32s2} -- this is an Espressif SoC with single Xtensa core. @item @code{esp32s3} -- this is an Espressif SoC with dual Xtensa cores. @item @code{fa526} -- resembles arm920 (w/o Thumb). |