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2024-05-01Remove old P extensionsAndrew Waterman1-2/+0
See https://github.com/riscv-software-src/riscv-isa-sim/pull/1660 for explanation
2023-02-27Removing all "grev" instances from "zbpbo" sub-extensionsBabu P S1-1/+0
GREV instruction no longer exist in the zbpbo specified by [v0.9.11 spec](https://github.com/riscv/riscv-p-spec/blob/master/P-ext-proposal.adoc#51-zbpbo)
2023-02-06Revert "Revert "updating opcodes of riscv-p-spec - v0.9.11 (c3409c8) (#147)""Andrew Waterman1-0/+1
This reverts commit 6b5a0648ab6b99507aef3c902afbcd3cd9d90353.
2023-02-05Revert "updating opcodes of riscv-p-spec - v0.9.11 (c3409c8) (#147)"Andrew Waterman1-1/+0
This reverts commit 9b0eddd52b9e3c1fbd1dab56ecbaa88747254a2a.
2022-12-07updating opcodes of riscv-p-spec - v0.9.11 (c3409c8) (#147)Babu P S1-0/+1
* Correction of riscv-p-spec opcodes - Reorganized 'p' into sub-extensions zpn, zpfs & zbpbo - Some instructions such as insb, smmul has been rearranged according XLEN. * removed rv_m in rv32_zbpbp + newline additions Co-authored-by: Babu P S <babu.ps@incoresemi.com>
2022-04-08migrate unratified bitmanip opcodesNeel Gala1-0/+2
- split instructions as per new file naming policy - move all instructions to unratified directory - includes rv[64|32]_zbp[bo] (missed in previous commit while migrating P-extension)