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2024-06-04Add unratified Smctr/Ssctr instructions and CSRs (#252)Ved Shanbhogue1-0/+1
2024-05-05Mark Zihintntl, Zicond, Zfa, Zbkb, and Zvbc as ratified (#246)Ved Shanbhogue13-60/+0
* Mark Zihintntl as ratified * Mark Zicond as ratified * Mark Zfa as ratified * Mark Zvbc as ratified * Mark Zbkb ratified * Mark xperm4/8 of Zbkx as ratified * Update Zbkb - remove Zbe
2024-05-05Mark Zimop and Zcmop ratified (#245)Ved Shanbhogue2-68/+0
2024-05-05Mark Zabha ratified (#244)Ved Shanbhogue1-23/+0
2024-05-01Remove remainder of B extensionsAndrew Waterman2-21/+0
Continuation of f0c6e9575f640e31a591b03f6bced408e9e08bac
2024-05-01Remove remainder of P extensionsAndrew Waterman2-39/+0
Continuation of e07ce62356e1f9a4497ec004fda5e6d5aadfcd48
2024-05-01Remove legacy bit-manipulation extensionsAndrew Waterman12-65/+0
These do not have a path to ratification. I left the ones that are generic versions of ratified instructions (e.g. orc.b is a special case of gorci).
2024-05-01Remove old P extensionsAndrew Waterman6-293/+0
See https://github.com/riscv-software-src/riscv-isa-sim/pull/1660 for explanation
2024-05-01Remove RV128 for nowAndrew Waterman2-38/+0
It is highly speculative at this point, but it adds maintenance burden.
2024-05-01Remove legacy bitmanip encodings that are now conflictingAndrew Waterman2-8/+0
Zbt (cmov) conflicts with ratified Zicond (czero.eqz) Zbm will conflict with soon-to-be-frozen Zpa
2024-03-01move opcode of zvb* (#236)Lucas9-179/+0
* move opcode of zvbb * move all zvk* out
2024-02-03Add Zicfilp codes (#225)mylai-mtk1-0/+2
2024-01-08Add missing `-n0` (#219)hirooih1-1/+1
add `_n0' on `rd` for `c.li`, `c.mv`, `c.add`, and `c.lqsp`. Signed-off-by: Hiroo HAYASHI <24754036+hirooih@users.noreply.github.com>
2023-12-23mark zacas ratifiedVed Shanbhogue2-3/+0
2023-11-25add zicfiss instructionsVed Shanbhogue1-0/+14
2023-11-25add compressed zicfiss instructionsVed Shanbhogue1-0/+5
2023-10-29Add Zabha AMO inst code pointsVed Shanbhogue1-0/+23
2023-10-19Making explicit that the aq bit is set for load-acquire, rl bit is set for ↵brs1-8/+8
store-releasee
2023-10-18Changing it so Zalasr has one bit hardcoded for each, to reduce opcode ↵brs1-8/+8
confusion hopefully
2023-10-18Adding load-acquire/store-release. Note they are written here as `lb.` for ↵brs1-0/+8
the load-acquire byte (so `lb.aq` and `lb.aqrl`), I'm not sure that will work but it passes the tests here.
2023-10-17Add pseudo-instructions for Zimop/Zcmop (#194)Ved Shanbhogue2-51/+57
* add mop.r.N and mop.rr.N pseudo-inst * add c.mop.N pseudo-inst * add arg_lut entries and emitted pseudoops for Zimop/Zcmop * add pseudoinsts for Zimop * add pseudoinsts for Zcmop * update zcmop mnemonics * update zcmop mnemonics
2023-09-20fix instruction duplication between rv128_c and rv64_cJiuyang Liu1-5/+5
2023-09-16Merge pull request #188 from charlie-rivos/fix_c_addiwAndrew Waterman1-3/+2
C.ADDIW cannot have an rd of 0
2023-09-15C.ADDIW cannot have an rd of 0Charlie Jenkins1-3/+2
The code point of rd=0 in C.ADDIW is restricted. Fix formatting while in these files. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
2023-09-15add unratified Zcmop instructionsVed Shanbhogue1-0/+13
2023-09-15add unratified Zimop instructionsVed Shanbhogue1-0/+49
2023-07-31rv64_q_zfa: rs2 is variable field.Nikola Rajovic1-1/+1
2023-07-31rv32_d_zfa: rs2 is variable field.Nikola Rajovic1-1/+1
2023-05-19Update encodings for vfwmaccbf16.vv/vfWeiwei Li1-2/+2
2023-05-13add amocas.q (RV64 only) zacas instructionVed Shanbhogue1-0/+1
2023-05-13add amocas.w/d zacas instructionsVed Shanbhogue1-0/+2
2023-05-01Support for Zvk, Vector Cryptography ExtensionsEric Gouriou12-4/+192
Add encodings for all instructions in the Zvk extensions: - Zvbb, Vector Bit-manipulation instructions used in Cryptography, - Zvbc, Vector Carryless Multiplication - Zvkg, Vector GCM/GMAC instruction for Cryptography, - Zvkned, NIST Suite: Vector AES Encryption & Decryption (Single Round), - Zvknha, Zvknhb, NIST Suite: Vector SHA-2, - Zvksed, ShangMi Suite: SM4 Block Cipher Instructions - Zvkssh, ShangMi Suite: SM3 Hash Function Instructions Add two "shorthand" extensions: - Zvkn: NIST Suite, imports Zvbb, Zvbc, Zvkned, and Zvknh - Zvks: ShangMi Suite, imports Zvbb, Zvbc, Zvksed, and Zvksh Three new fields are listed in constants.py: - 'zimm5', used to encode round constants (Zvkns, Zvksed, Zvksh), and 5-bit shift constant (vwsll.vi in Zvbb) - 'zimm6hi, zimm6lo', used to encode the 6 bits rotate amount in vror.vi. The Zvk instructions – with the exception of Zvbb, Zvbc – reside in the P opcode space. Some encodings conflict with proposed instructions in the P extension (packed SIMD). Zvk and P are exclusive of each other, no implementation will implement both. Conflicting P instructions are marked as pseudo of the Zvk instructions. The encodings match the current documentation of the specification at <https://github.com/riscv/riscv-crypto/tree/master/doc/vector>, at Version v0.9.1, 25 April, 2023 (Freeze Candidate). Co-authored-by: Eric Gouriou <ego@rivosinc.com> Co-authored-by: Stanislaw Kardach <kda@semihalf.com> Co-authored-by: Kornel Duleba <mindal@semihalf.com> Co-authored-by: Raghav Gupta <rgupta@rivosinc.com> Signed-off-by: Eric Gouriou <ego@rivosinc.com>
2023-04-15Add (unratified) BF16(Zfbfmin/Zvfbfmin/Zvfbfwma) extensions.Weiwei Li3-0/+6
2023-03-17Add (unratified) Zfa extensionPhilipp Tomsich6-0/+33
Zfa adds 'missing' floating-point functionality: - fli.[hsdq]: floating-point load-immediate - fminm/fmaxm.[hsdq]: IEEE 754-2019 minimum and maximum - fround(nx)?.[hsdq]: IEEE 754-2019 roundToIntegral(Exact)? - fcvtmod.w.d: ECMAScript modular float->integer conversion - move instructions for XLEN < FLEN - comparisons that support quiet NaN inputs This adds a surprisingly large number of files, as the instructions added with Zfa depend on context (e.g., .h-variants become available only if Zfh is present).
2023-03-16Add Smrnmi MNRET instructionAndrew Waterman1-0/+1
Forgot to add this as part of #168.
2023-02-27Removing all "grev" instances from "zbpbo" sub-extensionsBabu P S3-3/+0
GREV instruction no longer exist in the zbpbo specified by [v0.9.11 spec](https://github.com/riscv/riscv-p-spec/blob/master/P-ext-proposal.adoc#51-zbpbo)
2023-02-14Move Zawrs to ratified folder (#162)ved-rivos1-2/+0
* Move Zawrs to ratified folder * Move Zawrs to ratified folder
2023-02-06Revert "Revert "Fix pack instruction in rv_zbpbo""Andrew Waterman1-1/+1
This reverts commit 24cba79065aa975ad91e92c5d59f2e1dafa5ab26.
2023-02-06Revert "Revert "Removing import of csrrs and crrci in rv_zpn""Andrew Waterman1-2/+0
This reverts commit 3485bbcda5509615e4d18708722d67871efb7eaf.
2023-02-06Revert "Revert "updating opcodes of riscv-p-spec - v0.9.11 (c3409c8) (#147)""Andrew Waterman10-330/+325
This reverts commit 6b5a0648ab6b99507aef3c902afbcd3cd9d90353.
2023-02-05Revert "updating opcodes of riscv-p-spec - v0.9.11 (c3409c8) (#147)"Andrew Waterman10-325/+330
This reverts commit 9b0eddd52b9e3c1fbd1dab56ecbaa88747254a2a.
2023-02-05Revert "Removing import of csrrs and crrci in rv_zpn"Andrew Waterman1-0/+2
This reverts commit 2cf6da8f9a370ee5c0012d4ae4f403c3d920d1e8.
2023-02-05Revert "Fix pack instruction in rv_zbpbo"Andrew Waterman1-1/+1
This reverts commit 115e4237407e8c02b945dfb12c086ee57200dd55.
2023-01-14adding pseudo_ops for shift-ops where the mnemonics remain the sameNeel Gala1-0/+3
2023-01-12Fix backwards incompatibility introduced by RV128 opcodes in #112Andrew Waterman1-4/+3
Adding RV128 shift opcodes changed what metadata we emit for SLLI, SRLI, and SRAI. Thus, downstream tooling that relies on these to connote the RV64 variants of these instructions is semantically affected. Fix by reverting SLLI etc. to being the RV64 variants.
2023-01-12Rename RV128 shamt to shamtqAndrew Waterman1-3/+3
This will reduce the chance that people pick the wrong shamt width.
2023-01-11Add (unratified) ZiCond extension (#152)Philipp Tomsich1-0/+3
2023-01-03Fix pack instruction in rv_zbpboBabu P S1-1/+1
pack instruction should be imported from zbe -- instead of zbp. Signed-off-by: Babu P S <11073327+eflaner@users.noreply.github.com>
2022-12-12Removing import of csrrs and crrci in rv_zpnBabu P S1-2/+0
Removing import of csrrs and crrci as the instruction's pseudo opcode for is already included. Signed-off-by: Babu P S <11073327+eflaner@users.noreply.github.com>
2022-12-07updating opcodes of riscv-p-spec - v0.9.11 (c3409c8) (#147)Babu P S10-330/+325
* Correction of riscv-p-spec opcodes - Reorganized 'p' into sub-extensions zpn, zpfs & zbpbo - Some instructions such as insb, smmul has been rearranged according XLEN. * removed rv_m in rv32_zbpbp + newline additions Co-authored-by: Babu P S <babu.ps@incoresemi.com>
generated by cgit v1.1 at 2024-06-29 03:26:10 +0000