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| author | Neel Gala <neelgala@incoresemi.com> | 2022-04-08 18:02:38 +0530 |
|---|---|---|
| committer | Neel Gala <neelgala@incoresemi.com> | 2022-04-08 20:11:59 +0530 |
| commit | cf2bef3f0e52f95f9dfc9ce4ac8ff8ced92a26ac (patch) | |
| tree | 977cc728b2ccb5e38484fd6cb83af34f83e8f8cb /rv_zicsr | |
| parent | cc1bc440b3e338b366674faff531c6ffadb9b239 (diff) | |
| download | riscv-opcodes-cf2bef3f0e52f95f9dfc9ce4ac8ff8ced92a26ac.zip riscv-opcodes-cf2bef3f0e52f95f9dfc9ce4ac8ff8ced92a26ac.tar.gz riscv-opcodes-cf2bef3f0e52f95f9dfc9ce4ac8ff8ced92a26ac.tar.bz2 | |
migrate Zicsr-Extension opcodes
- renamed the variable imm12 to csr to match the latex-table entries.
Diffstat (limited to 'rv_zicsr')
| -rw-r--r-- | rv_zicsr | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/rv_zicsr b/rv_zicsr new file mode 100644 index 0000000..5c3e338 --- /dev/null +++ b/rv_zicsr @@ -0,0 +1,7 @@ +csrrw rd rs1 csr 14..12=1 6..2=0x1C 1..0=3 +csrrs rd rs1 csr 14..12=2 6..2=0x1C 1..0=3 +csrrc rd rs1 csr 14..12=3 6..2=0x1C 1..0=3 +csrrwi rd csr zimm 14..12=5 6..2=0x1C 1..0=3 +csrrsi rd csr zimm 14..12=6 6..2=0x1C 1..0=3 +csrrci rd csr zimm 14..12=7 6..2=0x1C 1..0=3 + |