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| author | Neel Gala <neelgala@incoresemi.com> | 2022-04-08 18:02:38 +0530 |
|---|---|---|
| committer | Neel Gala <neelgala@incoresemi.com> | 2022-04-08 20:11:59 +0530 |
| commit | cf2bef3f0e52f95f9dfc9ce4ac8ff8ced92a26ac (patch) | |
| tree | 977cc728b2ccb5e38484fd6cb83af34f83e8f8cb | |
| parent | cc1bc440b3e338b366674faff531c6ffadb9b239 (diff) | |
| download | riscv-opcodes-cf2bef3f0e52f95f9dfc9ce4ac8ff8ced92a26ac.zip riscv-opcodes-cf2bef3f0e52f95f9dfc9ce4ac8ff8ced92a26ac.tar.gz riscv-opcodes-cf2bef3f0e52f95f9dfc9ce4ac8ff8ced92a26ac.tar.bz2 | |
migrate Zicsr-Extension opcodes
- renamed the variable imm12 to csr to match the latex-table entries.
| -rw-r--r-- | opcodes-system | 8 | ||||
| -rw-r--r-- | rv_zicsr | 7 |
2 files changed, 7 insertions, 8 deletions
diff --git a/opcodes-system b/opcodes-system index aa26e38..1721905 100644 --- a/opcodes-system +++ b/opcodes-system @@ -1,14 +1,6 @@ # SYSTEM -ecall 11..7=0 19..15=0 31..20=0x000 14..12=0 6..2=0x1C 1..0=3 -ebreak 11..7=0 19..15=0 31..20=0x001 14..12=0 6..2=0x1C 1..0=3 sret 11..7=0 19..15=0 31..20=0x102 14..12=0 6..2=0x1C 1..0=3 mret 11..7=0 19..15=0 31..20=0x302 14..12=0 6..2=0x1C 1..0=3 dret 11..7=0 19..15=0 31..20=0x7b2 14..12=0 6..2=0x1C 1..0=3 sfence.vma 11..7=0 rs1 rs2 31..25=0x09 14..12=0 6..2=0x1C 1..0=3 wfi 11..7=0 19..15=0 31..20=0x105 14..12=0 6..2=0x1C 1..0=3 -csrrw rd rs1 imm12 14..12=1 6..2=0x1C 1..0=3 -csrrs rd rs1 imm12 14..12=2 6..2=0x1C 1..0=3 -csrrc rd rs1 imm12 14..12=3 6..2=0x1C 1..0=3 -csrrwi rd rs1 imm12 14..12=5 6..2=0x1C 1..0=3 -csrrsi rd rs1 imm12 14..12=6 6..2=0x1C 1..0=3 -csrrci rd rs1 imm12 14..12=7 6..2=0x1C 1..0=3 diff --git a/rv_zicsr b/rv_zicsr new file mode 100644 index 0000000..5c3e338 --- /dev/null +++ b/rv_zicsr @@ -0,0 +1,7 @@ +csrrw rd rs1 csr 14..12=1 6..2=0x1C 1..0=3 +csrrs rd rs1 csr 14..12=2 6..2=0x1C 1..0=3 +csrrc rd rs1 csr 14..12=3 6..2=0x1C 1..0=3 +csrrwi rd csr zimm 14..12=5 6..2=0x1C 1..0=3 +csrrsi rd csr zimm 14..12=6 6..2=0x1C 1..0=3 +csrrci rd csr zimm 14..12=7 6..2=0x1C 1..0=3 + |