riscv-isa-manual.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2017-05-07	user spec -> 2.2; priv spec -> 1.10	Andrew Waterman	1	-1/+1
2017-05-07	Remove SBI chapter	Andrew Waterman	1	-0/+2
2017-05-07	Add missing preface note	Andrew Waterman	1	-0/+2
2017-05-06	Clarified expected use of XS to summarize additional extension	Krste Asanovic	1	-0/+2
2017-05-05	Attempt to explain SEIP discipline	Andrew Waterman	1	-0/+2
2017-04-11	SPTBR -> SATP	Andrew Waterman	1	-2/+4
2017-03-29	Add PMP to preface	Andrew Waterman	1	-0/+1
2017-03-28	Renamed mbadbits to mtval (for "Trap Value") to be more generic name for regi...	Krste Asanovic	1	-1/+1
2017-03-28	Add preface entry for page fault cause renumbering	Andrew Waterman	1	-0/+4
2017-03-26	Replaced mbadaddr with mbadbits register, which can now capture bad	Krste Asanovic	1	-0/+4
2017-03-21	Added rationale for removal of machine-mode base-and-bounds schemes for now.	Krste Asanovic	1	-2/+9
2017-03-20	Changed mvendorid to hold the JEDEC manufacturer code for the core vendor as ...	Krste Asanovic	1	-2/+5
2017-03-20	Now mideleg /medeleg only exist if lower privilege mode exists and can take t...	Krste Asanovic	1	-0/+3
2017-03-20	Removed explicit convention on shadow CSRs.	Krste Asanovic	1	-3/+5
2017-03-20	Add changelog entries for PUM -> SUM and MXR	Andrew Waterman	1	-0/+3
2017-03-19	fix typo	Andrew Waterman	1	-2/+2
2017-03-19	Excised H-mode from spec.	Krste Asanovic	1	-12/+18
2017-03-19	Fixed up licence and contributor details on front page.	Krste Asanovic	1	-2/+6
2017-03-16	Simplify interrupt-stack discipline	Andrew Waterman	1	-0/+1
2017-02-24	Incorporate most of Hauser's feedback	Andrew Waterman	1	-0/+4
2017-02-20	mhcounteren -> mcounteren; mucounteren -> scounteren	Andrew Waterman	1	-0/+2
2017-02-19	Make hardware management of A/D bits optional	Andrew Waterman	1	-0/+3
2017-02-14	Add priv-1.10 preface	Andrew Waterman	1	-0/+14
2017-02-01	Reorganize directory structure	Andrew Waterman	1	-0/+20